- 您现在的位置：买卖IC网 > PDF目录1253 > XGBE-XGXS-O4-N2 (Lattice Semiconductor Corporation)IP CORE 10GBE ETHERNET XGXS PDF资料下载
参数资料
| 型号： | XGBE-XGXS-O4-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 3/38页 |
| 文件大小： | 0K |
| 描述： | IP CORE 10GBE ETHERNET XGXS |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | XGBEXGXSO4N2 |
第1页第2页当前第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页
Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
The ORT82G5 is a high-speed transceiver with an aggregate bandwidth of up to 29.6Gbits/s that is targeted
towards users in need of high-speed backplane and chip-to-chip interfaces using Ethernet and Fibre-Channel
based protocols. The ORT82G5 has eight channels of integrated 0.6-3.7Gbits/s SERDES channels that can be
used as 2x10Gbits/s XAUI interfaces.
XAUI is a high-speed interconnect that offers reduced pin count and is speci ? ed to drive up to 20 inches of PCB
trace on standard FR-4 material. Each XAUI interface comprises four self-timed 8b/10b encoded serial lanes each
operating at 3.125Gbits/s and thus is capable of transferring data at an aggregate rate of 10Gbits/s.
XGMII is a 156MHz Double Data Rate (DDR), parallel, short-reach interconnect interface (typically less than two
inches). It supports interfacing to 10Gbits/s Ethernet Media Access Control (MAC) and PHY devices.
In this design, the XGXS core is implemented in the FPGA portion of the device. A packet generator/checker and
MDIO interface are also implemented in the FPGA logic.
The XGXS IP core is provided with implementation scripts, test benches, and documentation to allow customers to
integrate the functions for 10GbE LAN/WAN applications.
XGXS Application Overview
The location of the XGXS in the 10GbE protocol stack is shown in Figure 1. A simpli ? ed block diagram of the
ORT82G5 XGXS solution is shown in Figure 2. The ORT82G5 with the XGXS IP implemented in the programma-
ble logic array provides the bridging capability to extend a standard 36-bit DDR XGMII across a XAUI-compatible
backplane.
Figure 1. XGXS Location in 10GbE Protocol Stack
Upper Layers
MAC Control (Optional)
Media Access Control ( MAC )
Reconciliation
XGMII – 10G Medium Independent Interface
XGXS – XAUI Extender Sublayer
XAUI – 10G Attachment Unit Interface
XSBI – 10G 16-Bit Interface
MDI – Medium Dependent Interface
*optional sublayer
Adding the WIS makes the WAN PHY
XGMII
XGXS*
XAUI
XGMII
XGXS*
XGMII/XAUI
64b/66b coding
Physical Coding Sublayer ( PCS )
WAN-compatible framing
WAN Interface Sublayer ( WIS )*
XSBI
Physical Medium Attachment ( PMA )
Physical Medium Dependent ( PMD )
MDI
Medium
3
16-bit parallel (OIF)
Retime, SERDES, CDR
E/O
相关PDF资料 |
PDF描述 |
|---|---|
| XM2D-0901 | CONNECTOR |
| XM2D-3701 | CONNECTOR |
| XM4M-2432-1312 | CONN DVI 24POS 1.5A 40V DIGITAL |
| XM4M-2932-1311 | CONN DVI 29POS 1.5A DIGTL/ANALOG |
| XM7B-0442 | CONN USB 1A 30VAC R/A WHITE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XGC | 制造商:Excelsys Technologies 功能描述:Power Suply, 36V@5.6A, Open Frame, Cage Mount, Modular, UltiMod Series 制造商:Excelsys Technologies 功能描述:MODULE POWER 28.8V-39.6V 5.6A |
| XGC10-88-S20 | 制造商:Johnson Electric / Saia-Burgess 功能描述:Catalogue / XGC10-88-S20 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XGC10-88-S20 |
| XGC11-88-S20 | 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XGC11-88-S20 |
| XGC11-88-S20Z1 | 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XGC11-88-S20Z1 |
| XGC11-88-S40 | 制造商:SAIA - BURGESS ELECTRONICS INC. 功能描述:Catalogue / XGC11-88-S40 |
发布紧急采购，3分钟左右您将得到回复。