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参数资料
| 型号： | XGBE-XGXS-O4-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 27/38页 |
| 文件大小： | 0K |
| 描述： | IP CORE 10GBE ETHERNET XGXS |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | XGBEXGXSO4N2 |
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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Figure 13. XGMII Timing Parameters
xgmii_txclk_156,
xgmii_rxclk_156,
t pwmin
t pwmin
V IH_AC(min)
xgmii_rxclk_156_out
V IL_AC(max)
xgmii_tx_data[31:0],
xgmii_tx_ctrl[3:0,
xgmii_rx_data[31:0],
xgmii_rx_ctrl[3:0]]
t setup
t hold
t setup
t hold
V IH_AC(min)
V IL_AC(max)
Symbol
t SETUP
t HOLD
t PWMIN
Driver
960
960
2.5
Receiver
480
480
—
Units
ps
ps
ns
XAUI Speci ? cations
The electrical characteristics of the XGXS XAUI signals conform to Clause 47.3 of IEEE 802.3ae. The general
XAUI driver requirements are given in Table 16. The XAUI driver template and receiver characteristics are given in
Figure 14 and Table 17, respectively. The XAUI SERDES interface circuit topology is shown in Table 15. Complete
speci ? cations on the SERDES may be found in the ORT82G5 Data Sheet.
Table 16. XAUI Driver Characteristics
Parameter
Baud rate tolerance
Unit interval nominal
Differential amplitude maximum
Absolute output voltage limits
Maximum
Minimum
Differential output return loss minimum
Output jitter
Near-end maximums
Total jitter
Deterministic jitter
Far-end maximums
Total jitter
Deterministic jitter
Value
3.125Gbd (100ppm
320
1600
2.3
-0.4
See Equation 1 1
± 0.175 peak from the mean
± 0.085 peak from the mean
± 0.275 peak from the mean
± 0.185 peak from the mean
Units
GBd ppm
ps
mVp-p
V
V
dB
UI
UI
UI
UI
1. Equation 1: s 11 = -10dB for 312.5MHz < Freq(f) < 625MHz, and
-10 + 10log (f/625)dB for 625MHz ≤ Freq(f) ≤ 3.125GHz
27
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