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参数资料
| 型号： | XGBE-XGXS-O4-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 31/38页 |
| 文件大小： | 0K |
| 描述： | IP CORE 10GBE ETHERNET XGXS |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | XGBEXGXSO4N2 |
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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Figure 17. Embedded Core <-> FPGA Receive Interface
Note: x = [AA, AB, , BD]
40
2:1
40
MRWDx
MULTIPLEXER
(X 40)
XAUI LINK
STATE
MACHINE
RWBIT8X[3:0]
36
1:4
DEMUX
RWDx[31:0]
(X 10)
DEMUX
RWBYTESYNC[3:0]
RWCKx
CHANNEL ALIGN
RSYS_CLK_(A1,A2,B1,B2)
RWCKx
4 CHANNELS
RCKSLE[1:0]
MUX
RCK78(A,B)
EMBEDDED CORE
FPGA
REFCLKP_[A:B], REFCLKN_[A:B]
REFCLKP_[A:B] and REFCLKN_[A:B] are differential reference clocks provided to the SERDES block in the
ORT82G5 device. There is a reference clock for each quad SERDES block in the design and it is used as the refer-
ence clock for both TX and RX paths. For the XAUI interface, these reference clocks are 156.25MHz.
RWCK[AA:BD]
RWCK[AA:BD] are the low-speed clocks from the embedded core to the FPGA across the core-FPGA interface.
These clocks are derived from the recovered low-speed complementary clocks from the SERDES blocks.
RWCK_BA belongs to Channel BA; RWCK_BB belongs to channel BB and so on. With a reference clock input of
156.25MHz and full rate mode, these clocks operate at 78MHz.
RCK78[A:B]
RCK78[A:B] are muxed outputs of RWCKA[A:D] and RWCKB[B:D] respectively. With a reference clock input of
156.25MHz, these clocks operate at 78MHz. For the XGXS IP core, the mux is set such that RCK78B is supplied
by RWCKBA.
RSYS_CLK_[A:B][1:2]
RSYS_CLK_[A:B][1:2] are inputs to the SERDES quad block A and B respectively from the FPGA. These are used
by each channel as the read clock to read data from the alignment FIFO within the embedded core. Clocks
RSYS_CLK_A[1:2] are used by channels in the SERDES quad block A and RSYS_CLK_B[1:2] by channels in the
SERDES quad block B. To guarantee that there is no over ? ow in the alignment FIFO, it is a requirement that the
write and read clocks are synchronous. The recommended clocking strategy is to use RCK78B from the core and
feed it to RSYS_CLK_B[1:2].
31
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