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参数资料
| 型号： | XQ4013E-4PG223M |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | FPGA, 576 CLBS, 10000 GATES, 111 MHz, CPGA223 |
| 封装： | CERAMIC, PGA-223 |
| 文件页数： | 16/36页 |
| 文件大小： | 294K |
| 代理商： | XQ4013E-4PG223M |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
2-65
Product Specification
1-800-255-7778
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XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000EX devices unless otherwise noted.
Symbol
Single Port RAM
Size
-4
Units
Min
Max
Write Operation
TWCS
Address write cycle time (clock K period)
16x2
11.0
-
ns
TWCTS
32x1
11.0
-
ns
TWPS
Clock K pulse width (active edge)
16x2
5.5
-
ns
TWPTS
32x1
5.5
-
ns
TASS
Address setup time before clock K
16x2
2.7
-
ns
TASTS
32x1
2.6
-
ns
TAHS
Address hold time after clock K
16x2
0
-
ns
TAHTS
32x1
0
-
ns
TDSS
DIN setup time before clock K
16x2
2.4
-
ns
TDSTS
32x1
2.9
-
ns
TDHS
DIN hold time after clock K
16x2
0
-
ns
TDHTS
32x1
0
-
ns
TWSS
WE setup time before clock K
16x2
2.3
-
ns
TWSTS
32x1
2.1
-
ns
TWHS
WE hold time after clock K
16x2
0
-
ns
TWHTS
32x1
0
-
ns
TWOS
Data valid after clock K
16x2
-
8.2
ns
TWOTS
32x1
-
10.1
ns
Notes:
1.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol
Dual Port RAM
Size(1)
-4
Units
Min
Max
Write Operation
TWCDS
Address write cycle time (clock K period)
16x1
11.0
ns
TWPDS
Clock K pulse width (active edge)
16x1
5.5
-
ns
TASDS
Address setup time before clock K
16x1
3.1
-
ns
TAHDS
Address hold time after clock K
16x1
0
-
ns
TDSDS
DIN setup time before clock K
16x1
2.9
-
ns
TDHDS
DIN hold time after clock K
16x1
0
-
ns
TWSDS
WE setup time before clock K
16x1
2.1
-
ns
TWHDS
WE hold time after clock K
16x1
0
-
ns
TWODS
Data valid after clock K
16x1
-
9.4
ns
Notes:
1.
Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
2.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
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