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参数资料
| 型号： | XQ4013E-4PG223M |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | FPGA, 576 CLBS, 10000 GATES, 111 MHz, CPGA223 |
| 封装： | CERAMIC, PGA-223 |
| 文件页数： | 25/36页 |
| 文件大小： | 294K |
| 代理商： | XQ4013E-4PG223M |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
2-73
Product Specification
1-800-255-7778
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FXQ4028EX IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values
apply to all XQ4000EX devices unless otherwise noted.
Symbol
Description
-4
Units
Min
Max
Propagation Delays (TTL Output Levels)
TOKPOF
Clock (OK) to pad, fast
-
7.4
ns
TOPF
Output (O) to pad, fast
-
6.2
ns
TTSHZ
3-state to pad High-Z, slew-rate independent
-
4.9
ns
TTSONF
3-state to pad active and valid, fast
-
6.2
ns
TOKFPF
Output MUX select (OK) to pad
-
6.7
ns
TCEFPF
Fast path output MUX input (EC) to pad
-
6.2
TOFPF
Slowest path output MUX input (EC) to pad
-
7.3
Setup and Hold Times
TOOK
Output (O) to clock (OK) setup time
0.6
-
ns
TOKO
Output (O) to clock (OK) hold time
0
-
ns
TECOK
Clock enable (EC) to clock (OK) setup
0
-
ns
TOKEC
Clock enable (EC) to clock (OK) hold
0
-
ns
Clocks
TCH
Clock High
3.5
-
ns
TCL
Clock Low
3.5
-
ns
Global Set/Reset
TMRW
Minimum GSR pulse width
13.0
-
ns
TRRI
Delay from GSR input to any pad
30.2
-
ns
Notes:
1.
Output timing is measured at TTL threshold, with 35 pF external capacitive loads.
2.
For CMOS output levels, see the "XQ4028EX Output Level and Slew Rate Adjustments" on page 69.
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