参数资料
型号: XQ4013E-4PG223M
厂商: XILINX INC
元件分类: FPGA
英文描述: Field Programmable Gate Array (FPGA)
中文描述: FPGA, 576 CLBS, 10000 GATES, 111 MHz, CPGA223
封装: CERAMIC, PGA-223
文件页数: 27/36页
文件大小: 294K
代理商: XQ4013E-4PG223M
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
1-800-255-7778
R
1
2
3
4
5
6
I/O
H16
P68
286
I/O
H17
P69
291
I/O
H18
P70
295
I/O
J18
P71
298
I/O
J17
P72
301
I/O_(/ERR_/INIT)
J16
P73
304
VCC
J15
P74
-
GND
K15
P75
-
I/O
K16
P76
307
I/O
K17
P77
310
I/O
K18
P78
313
I/O
L18
P79
316
I/O
L17
P80
319
I/O
L16
P81
322
I/O
M18
P82
325
I/O
M17
P83
328
I/O
N18
P84
331
I/O
P18
P85
334
GND
M16
P86
-
I/O
N17
P87
337
I/O
R18
P88
340
I/O
T18
P89
343
I/O
P17
P90
349
I/O
N16
P91
349
I/O
T17
P92
352
I/O
R17
P93
355
I/O
P16
P94
358
I/O
U18
P95
361
SGCK3_(I/O)
T16
P96
364
GND
R16
P97
-
DONE
U17
P98
-
VCC
R15
P99
-
/PROG
V18
P100
-
I/O_(D7)
T15
P101
367
Pin Description
PG191
CB196
Bound
Scan
Notes:
1.
Indicates unconnected package pins.
2.
Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
PGCK3_(I/O)
U16
P102
370
--
P103(1)
-
I/O
T14
P104
376
I/O
U15
P105
376
I/O_(D6)
V17
P106
379
I/O
V16
P107
382
I/O
T13
P108
385
I/O
U14
P109
388
I/O
V15
P110
391
I/O
V14
P111
394
GND
T12
P112
-
I/O
U13
P113
397
I/O
V13
P114
400
I/O_(D5)
U12
P115
403
I/O_(/CSO)
V12
P116
406
I/O
T11
P117
409
I/O
U11
P118
412
I/O
V11
P119
415
I/O
V1
P120
418
I/O_(D4)
U10
P121
421
I/O
T10
P122
424
VCC
R10
P123
-
GND
R9
P124
-
I/O_(D3)
T9
P125
427
I/O_(/RS)
U9
P126
430
I/O
V9
P127
433
I/O
V8
P128
436
I/O
U8
P129
439
I/O
T8
P130
442
I/O_(D2)
V7
P131
445
I/O
U7
P132
448
I/O
V6
P133
451
I/O
U6
P134
454
GND
T7
P135
-
Pin Description
PG191
CB196
Bound
Scan
Notes:
1.
Indicates unconnected package pins.
2.
Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
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