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参数资料
| 型号： | XQ4013E-4PG223M |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | FPGA, 576 CLBS, 10000 GATES, 111 MHz, CPGA223 |
| 封装： | CERAMIC, PGA-223 |
| 文件页数： | 9/36页 |
| 文件大小： | 294K |
| 代理商： | XQ4013E-4PG223M |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
2-59
Product Specification
1-800-255-7778
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XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are not
measured directly. They are derived from benchmark timing
patterns that are taken at device introduction, prior to any
process improvements. For more detailed, more precise,
and more up-to-date information, use the values provided
by the XACT timing calculator and used in the simulator.
These values can be printed in tabular format by running
LCA2XNF-S.
The following guidelines reflect worst-case values over the
recommended operating conditions. They are expressed in
units of nanoseconds and apply to all XC4000E devices
unless otherwise noted.
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Units
Symbol
Description
Min
Max
Min
Max
Setup Times
TTDITCK
Input (TDI) to clock (TCK)
30.0
ns
TTMSTCK
Input (TMS) to clock (TCK)
15.0
ns
Hold Times
TTCKTDI
Input (TDI) to clock (TCK)
0
ns
TTCKTMS
Input (TMS) to clock (TCK)
0
ns
Propagation Delay
TTCKPO
Clock (TCK) to pad (TDO)
30.0
ns
Clock
TTCKH
Clock (TCK) High
5.0
ns
TTCKL
Clock (TCK) Low
5.0
ns
FMAX
Frequency
15.0
MHz
Notes:
1.
Input setup and hold times and clock-to-pad times are specified with respect to external signal pins.
2.
Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall
times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the
“Additional XC4000 Data” section of the Programmable Logic Data Book.
3.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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