参数资料
型号: XQ4013E-4PG223M
厂商: XILINX INC
元件分类: FPGA
英文描述: Field Programmable Gate Array (FPGA)
中文描述: FPGA, 576 CLBS, 10000 GATES, 111 MHz, CPGA223
封装: CERAMIC, PGA-223
文件页数: 8/36页
文件大小: 294K
代理商: XQ4013E-4PG223M
QPRO XQ4000E/EX QML High-Reliability FPGAs
2-58
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification
R
XQ4000E IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values
apply to all XQ4000E devices unless otherwise noted.
Symbol
Description
-3
-4
Units
Min
Max
Min
Max
Propagation Delays (TTL Output Levels)
TOKPOF
Clock (OK) to pad, fast
-
6.5
-
7.5
ns
TOKPOS
Clock (OK) to pad, slew-rate limited
-
9.5
-
11.5
ns
TOPF
Output (O) to pad, fast
-
5.5
-
8.0
ns
TOPS
Output (O) to pad, slew-rate limited
-
8.6
-
12.0
ns
TTSHZ
3-state to pad High-Z, slew-rate independent
-
4.2
-
10.0
ns
TTSONF
3-state to pad active and valid, fast
-
8.1
-
10.0
ns
TTSONS
3-state to pad active and valid, slew-rate limited
-
11.1
-
13.7
ns
Propagation Delays (CMOS Output Levels)
TOKPOFC Clock (OK) to pad, fast
-
7.8
-
9.5
ns
TOKPOSC Clock (OK) to pad, slew-rate limited
-
11.6
-
13.5
ns
TOPFC
Output (O) to pad, fast
-
9.7
-
10.0
ns
TOPSC
Output (O) to pad, slew-rate limited
-
13.4
-
14.0
ns
TTSHZC
3-state to pad High-Z, slew-rate independent
-
4.3
-
5.2
ns
TTSONFC
3-state to pad active and valid, fast
-
7.6
-
9.1
ns
TTSONSC 3-state to pad active and valid, slew-rate limited
-
11.4
-
13.1
ns
Setup and Hold Times
TOOK
Output (O) to clock (OK) setup time
4.6
-
5.0
-
ns
TOKO
Output (O) to clock (OK) hold time
0
-
0
-
ns
TECOK
Clock enable (EC) to clock (OK) setup
3.5
-
4.8
-
ns
TOKEC
Clock enable (EC) to clock (OK) hold
1.2
-
1.2
-
ns
Clock
TCH
Clock High
4.0
-
4.5
-
ns
TCL
Clock Low
4.0
-
4.5
-
ns
Global Set/Reset(3)
TRRO
Delay from GSR net to pad
-
11.8
-
15.0
ns
TMRW
GSR width
11.5
-
13.0
-
ns
TMRO
GSR inactive to first active clock (OK) edge
11.5
-
13.0
-
ns
Notes:
1.
Output timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall
times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the
“Additional XC4000 Data” section on the Xilinx web site, www.xilinx.com/partinfo/databook.htm.
2.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
3.
Timing is based on the XC4005E. For other devices see the XACT timing calculator.
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