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参数资料
| 型号： | XQ4013E-4PG223M |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | FPGA, 576 CLBS, 10000 GATES, 111 MHz, CPGA223 |
| 封装： | CERAMIC, PGA-223 |
| 文件页数： | 6/36页 |
| 文件大小： | 294K |
| 代理商： | XQ4013E-4PG223M |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
2-56
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification
R
XQ4000E IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values apply to all XQ4000E devices
unless otherwise noted.
Symbol
Description
Device
-3
-4
Units
Min
Max
Min
Max
Propagation Delays (TTL Inputs)(1)
TPID
Pad to I1, I2
All devices
-
2.5
-
3.0
ns
TPLI
Pad to I1, I2 via transparent input latch, no delay
All devices
-
3.6
-
4.8
ns
TPDLI
Pad to I1, I2 via transparent FCL and input latch,
with delay
XQ4005E
-
10.8
ns
XQ4010E
-
10.8
-
11.0
ns
XQ4013E
-
11.2
-
11.4
ns
XQ4025E
-
13.8
ns
Propagation Delays (CMOS Inputs)(1)
TPIDC
Pad to I1, I2
All devices
-
4.1
-
5.5
ns
TPLIC
Pad to I1, I2 via transparent input latch, no delay
All devices
-
8.8
-
6.8
ns
TPDLIC
Pad to I1, I2 via transparent FCL and input latch,
with delay
XQ4005E
-
16.5
ns
XQ4010E
-
14.0
-
17.5
ns
XQ4013E
-
14.4
-
18.0
ns
XQ4025E
-
20.8
ns
Propagation Delays (TTL Inputs)
TIKRI
Clock (IK) to I1, I2 (flip-flop)
All devices
-
2.8
-
5.6
ns
TIKLI
Clock (IK) to I1, I2 (latch enable, active Low)
All devices
-
4.0
-
6.2
ns
Hold Times(2)
TIKPI
Pad to clock (IK), no delay
All devices
0
-
0
-
ns
TIKPID
Pad to clock (IK), with delay
All devices
0
-
0
-
ns
TIKEC
Clock enable (EC) to clock (K), no delay
All devices
1.5
-
1.5
-
ns
TIKECD
Clock enable (EC) to clock (K), with delay
All devices
0
-
0
-
ns
Notes:
1.
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
2.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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