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参数资料
| 型号： | XQ4013E-4PG223M |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | FPGA, 576 CLBS, 10000 GATES, 111 MHz, CPGA223 |
| 封装： | CERAMIC, PGA-223 |
| 文件页数： | 32/36页 |
| 文件大小： | 294K |
| 代理商： | XQ4013E-4PG223M |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
2-47
Product Specification
1-800-255-7778
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XQ4000E Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4000E devices unless otherwise noted.
The following guidelines reflect worst-case values over the
recommended operating conditions.
Symbol
Description
Device
-3
-4
Units
Max
TBUF Driving a Horizontal Longline (LL):
TIO1
I going High or Low to LL going High or Low, while T is Low.
Buffer is constantly active.(1)
XQ4005E
-
5.0
ns
XQ4010E
6.4
8.0
ns
XQ4013E
7.2
9.0
ns
XQ4025E
-
11.0
ns
TIO2
I going Low to LL going from resistive pull-up High to active Low.
TBUF configured as open-drain.(1)
XQ4005E
-
6.0
ns
XQ4010E
6.9
10.5
ns
XQ4013E
7.7
11.0
ns
XQ4025E
-
12.0
ns
TON
T going Low to LL going from resistive pull-up or floating High to
active Low. TBUF configured as open-drain or active buffer with
I = Low.(1)
XQ4005E
-
7.0
ns
XQ4010E
7.3
8.5
ns
XQ4013E
7.5
8.7
ns
XQ4025E
-
11.0
ns
TOFF
T going High to TBUF going inactive, not driving LL.
XQ4005E
-
1.8
ns
XQ4010E
1.5
1.8
ns
XQ4013E
1.5
1.8
ns
XQ4025E
-
1.8
ns
TPUS
T going High to LL going from Low to High, pulled up by a single
resistor.(1)
XQ4005E
-
23.0
ns
XQ4010E
22.0
29.0
ns
XQ4013E
26.0
32.0
ns
XQ4025E
-
42.0
ns
TPUF
T going High to LL going from Low to High, pulled up by two
resistors.(1)
XQ4005E
-
10.0
ns
XQ4010E
11.0
13.5
ns
XQ4013E
13.0
15.0
ns
XQ4025E
-
18.0
ns
Notes:
1.
These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.
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