
XRT94L33
xr
Rev.1.2.0.
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
28
C7
TXPOH
I
TTL
Transmit Path Overhead Input Port – Input pin.
This pin is used for the Transmit AU-4/VC-4 Mapper POH
Processor Block when TUG-3 mapping is used.
This input pin permits the user to insert the POH data into the
Transmit AU-4/VC-4 Mapper POH Processor blocks for
insertion and transmission via the “outbound” STS-3 signal.
In this mode, the external circuitry (which is being interfaced to
the “Transmit Path Overhead Input Port” is suppose to monitor
the following output pins;
TxPOHFrame_n
TxPOHEnable_n
TxPOHClk_n
The “TxPOHFrame_n” output pin will toggle “high” upon the
rising
edge
of
“TxPOHClk_n”
approximately
one
“TxPOHClk_n” period prior to the “TxPOH” port being ready to
accept and process the first bit within J1 byte (e.g., the first
POH byte).
The “TxPOHFrame_n” output pin will remain
“high” for eight consecutive “TxPOHClk_n” periods.
The
external circuitry should use this pin to note STS-1 SPE frame
boundaries.
The “TxPOHEnable_n” output pin will toggle “high” upon the
rising
edge
of
“TxPOHClk_n”
approximately
one
“TxPOHClk_n” period prior to the “TxPOH” port being ready to
accept and process the first bit within a given POH byte. To
externally insert a given POH byte:
(1) assert the “TxPOHIns_n” input pin by toggling it
“high”, and
(2) place the value of the first bit (within this particular
POH byte) on this input pin upon the very next rising
edge of “TxPOHClk_n”.
This data bit will be sampled upon the very next falling edge of
“TxPOHClk_n”. The external circuitry should continue to keep
the “TxPOHIns_n” input pin “high” and advancing the next bits
(within
the
POH
bytes)
upon
each
rising
edge
of
“TxPOHClk_n”.
D9
TXPOHCLK
O
TTL
Transmit Path Overhead Input Port – Clock Output pin:
This pin is used for the Transmit AU-4/VC-4 Mapper POH
Processor Block when TUG-3 mapping is used.
This
output
pin,
along
with
“TxPOH”,
“TxPOHEnable”,
“TxPOHIns” and “TxPOHFrame” function as the “Transmit
Path Overhead (TxPOH) Input Port”.
The “TxPOHFrame” and “TxPOHEnable” output pins are
updated upon the falling edge this clock output signal. The
“TxPOHIns” input pins and the data residing on the “TxPOH”
input pins are sampled upon the next falling edge of this clock
signal.