
XRT94L33
xr
Rev.1.2.0.
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
286
STEP 2 – Begin providing the values of the “outbound” Z3 byte to the “TxPOH_n” input port.
The procedure for applying the Z3 byte to the “TxPOH_n” input port is presented below.
Using the “TxPOH” Input Port to insert the Z3 byte value into the outbound STS-1 SPE data-stream
If the user intends to externally insert the Z3 byte into the outbound STS-1 SPE, via the “TxPOH_n” input port,
then they must design some external circuitry (which can be realized in an ASIC, FPGA or CPLD solution) to
do to the following.
Continuously sample the “TxPOHEnable_n” and the “TxPOHFrame_n” output pins upon the rising edge of
the “TxPOHClk_n” output clock signal.
A simple illustration of this “external circuit” being interfaced to the “TxPOH Input Port” is presented below in
Figure 54 : A Simple Illustration of the “External Circuit” being interfaced to the “TxPOH Input Port”
TxPOH_n
TxPOHClk_n
TxPOHFrame_n
TxPOHEnable_n
TxPOHIns_n
XRT95L34 Device
External Circuit
TxPOHClk_IN
TxPOHFrame_IN
TxPOHData_OUT
TxPOHEnable_IN
TxPOH_INSERT
Note:
The “TxPOHIns_n” line (i
nFigure 54) is “dashed” because controlling this signal is not necessary if the user has
Whenever the “external circuit” samples both the “TxPOHEnable_n” and “TxPOHFrame_n” output pins
“high”, then it should enter a “WAIT STATE” (e.g., where it will wait for 48 periods of “TxPOHClk_n” to
elapse). Afterwards, the external circuit should exit this “WAIT STATE” and then place the very first bit (e.g.,
the most significant bit) of the “outbound” Z3 byte onto the “TxPOH_n” input pin, upon the very next falling
edge of “TxPOHClk_n”. This data bit will be sampled and latched into the “Transmit SONET POH Processor”
block circuitry, upon the very next rising edge of “TxPOHClk_n”.
Note:
This “WAIT STATE” period is necessary because the Z3 byte is the seventh byte within the POH.
Afterwards, the “external circuit” should serially place the remaining seven bits (of the Z3 byte) onto the
“TxPOH_n” input pin, upon each of the next seven falling edges of “TxPOHClk_n”.
The “external circuit” should then revert back to continuously sampling the states of the “TxPOHEnable_n”
and “TxPOHFrame_n” output pins and repeat the above-mentioned process.