
xr
XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
409
If the HEC Byte Verification Block detects a Single-Bit Error within the Header bytes of an ATM Cell:
1. It will generate the “Detection of Correctable HEC Byte Error” Interrupt. The Receive ATM Cell Processor
block will indicate that it is declaring the “Detection of Correctable HEC Byte Error” Interrupt, by doing the
following.
a.
Toggling the “INT*” output pin “low”.
b.
Setting Bit 3 (Detection of Correctable HEC Byte Error Interrupt Status), within the “Receive ATM Cell
Processor Block – Receive ATM Interrupt Status Register – Byte 0” to “1” as depicted below.
Receive ATM Cell Processor Block – Receive ATM Interrupt Status Register – Byte 0 (Address =
0xN70B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
Cell
Insertion
Interrupt
Status
Receive
FIFO
Overflow
Interrupt
Status
Receive
Cell
Extraction
Memory
Overflow
Interrupt
Status
Receive
Cell
Insertion
Memory
Overflow
Interrupt
Status
Detection of
Correctable
HEC Byte
Error
Interrupt
Status
Detection of
Uncorrectable
HEC Byte
Error Interrupt
Status
Clearance
of LCD
Defect
Interrupt
Status
Declaration
of LCD
Defect
Interrupt
Status
RUR
0
1
0
2. It will increment the “Receive ATM Cell Processor Block – Receive ATM Cell with Correctable HEC Byte
Error Count” Registers. This is 32-bit RESET-upon-READ register that resides at Address Locations 0xN730
through 0xN733. The bit format of these registers is presented below.
Receive ATM Cell Processor Block – Receive ATM Cells with Correctable HEC Byte Error Count
Register – Byte 3 (Address = 0xN730)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Received Cells with Correctable HEC Byte Error Count[31:24]
RUR
0
Receive ATM Cell Processor Block – Receive ATM Cells with Correctable HEC Byte Error Count
Register – Byte 2 (Address = 0xN731)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Received Cells with Correctable HEC Byte Error Count[23:16]
RUR
0
Receive ATM Cell Processor Block – Receive ATM Cells with Correctable HEC Byte Error Count
Register – Byte 1 (Address = 0xN732)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Received Cells with Correctable HEC Byte Error Count[15:8]
RUR
0
Receive ATM Cell Processor Block – Receive ATM Cells with Correctable HEC Byte Error Count
Register – Byte 0 (Address = 0xN733)