参数资料
型号: ZL2008ALAFT
厂商: Intersil
文件页数: 11/42页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 36-QFN
标准包装: 100
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 95%
电源电压: 3 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL2008
Power Conversion Overview
The ZL2008 operates as a voltage-mode, synchronous buck
converter with a selectable constant frequency pulse width
modulator (PWM) control scheme that uses external MOSFETs,
capacitors, and an inductor to perform power conversion.
V IN
Typically, buck converters specify a maximum duty cycle that
effectively limits the maximum output voltage that can be
realized for a given input voltage. This duty cycle limit ensures
that the lowside MOSFET is allowed to turn on for a minimum
amount of time during each switching cycle, which enables the
bootstrap capacitor (CB in Figure 5) to be charged up and provide
adequate gate drive voltage for the high-side MOSFET. See
section“High-side Driver Boost Circuit” on page 12 for more
VR
ZL
BST
GH
SW
GL
DB
CB
QH
QL
C IN
V OUT
C OUT
details.
In general, the size of components L1 and C OUT as well as the
overall efficiency of the circuit are inversely proportional to the
switching frequency, f SW . Therefore, the highest efficiency circuit
may be realized by switching the MOSFETs at the lowest possible
frequency; however, this will result in the largest component size.
Conversely, the smallest possible footprint may be realized by
D ≈
V OUT
FIGURE 5. Synchronous Buck Converter
Figure 5 illustrates the basic synchronous buck converter
topology showing the primary power train components. This
converter is also called a step-down converter, as the output
voltage must always be lower than the input voltage. In its most
simple configuration, the ZL2008 requires two external N-
channel power MOSFETs, one for the top control MOSFET (QH)
and one for the bottom synchronous MOSFET (QL). The amount
of time that QH is on as a fraction of the total switching period is
known as the duty cycle D , which is described by Equation 1:
(EQ. 1)
V IN
During time D, QH is on and V IN – V OUT is applied across the
inductor. The current ramps up as shown in Figure 6.
When QH turns off (time 1-D), the current flowing in the inductor
must continue to flow from the ground up through QL, during
which the current ramps down. Since the output capacitor C OUT
exhibits a low impedance at the switching frequency, the AC
component of the inductor current is filtered from the output
voltage so the load sees nearly a DC voltage.
V IN - V OUT
IL PK
switching at the fastest possible frequency but this gives a
somewhat lower efficiency. Each user should determine the
optimal combination of size and efficiency when determining the
switching frequency for each application.
The block diagram for the ZL2008 is illustrated in Figure 4. In
this circuit, the target output voltage is regulated by connecting
the differential VSEN pins directly to the output regulation point.
The VSEN signal is then compared to a reference voltage that has
been set to the desired output voltage level by the user. The error
signal derived from this comparison is converted to a digital
value with a low-resolution, analog to digital (A/D) converter. The
digital signal is applied to an adjustable digital compensation
filter, and the compensated signal is used to derive the
appropriate PWM duty cycle for driving the external MOSFETs in a
way that produces the desired output.
The ZL2008 has several features to improve the power
conversion efficiency. A non-linear response (NLR) loop improves
the response time and reduces the output deviation as a result of
a load transient. The ZL2008 monitors the power converter’s
operating conditions and continuously adjusts the turn-on and
turn-off timing of the high-side and low-side MOSFETs to optimize
the overall efficiency of the power supply. Adaptive performance
optimization algorithms such as dead-time control, diode
emulation, and frequency control are available to provide greater
efficiency improvement.
Power Management Overview
The ZL2008 incorporates a wide range of configurable power
management features that are simple to implement with no
external components. Additionally, the ZL2008 includes circuit
0
I O
protection features that continuously safeguard the device and
load from damage due to unexpected system faults. The ZL2008
can continuously monitor input voltage, output voltage/current,
internal temperature, and the temperature of an external
-V OUT
D 1-D
Time
FIGURE 6. Inductor Waveform
11
IL V
thermal diode. A Power Good output signal is also included to
enable power-on reset functionality for an external processor.
All power management functions can be configured using either
pin configuration techniques (see Figure 7) or via the I 2 C/SMBus
interface. Monitoring parameters can also be pre-configured to
provide alerts for specific conditions. See Application Note
AN2033 for more details on SMBus monitoring.
FN6859.4
April 29, 2011
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ZL2008ALAFT1 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP(0.300",7.62mm) 包装:管件 产品目录页面:1316 (CN2011-ZH PDF)
ZL2008ALBFT 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
ZL2008ALBFT1 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
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