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| 型号： | ZL2008ALAFT |
| 厂商： | Intersil |
| 文件页数： | 36/42页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 36-QFN |
| 标准包装： | 100 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ZL2008
dropped or faults then the device with the next lowest position
number will become the new reference device.
SYNC Clock (CFG1 Pin)
Typically the reference device sources the SYNC clock. However,
DDC
SDA
SCL
SYNC
3.3V
DEV_1
0x20
REF.
POS_1
POS_0
SYNC_Out
VCC
PH_1
Rail_1
Rail DDC ID = 5
Rout Cout
any device internal or external to the current sharing group can
source the SYNC clock. If the reference device is sourcing the
SYNC clock, then resistor pin-strap the CFG1 pin to configure the
SYNC pin as an output. Otherwise configure the reference
device’s SYNC pin as an input. For member devices, resistor
pin-strap the CFG1 pin to configure the SYNC pin as an input.
Soft-start (SS Pin)
DEV_2
0x21
POS_1
MEM_1
POS_2
SYNC_In
DEV_3
0x22
POS_2
MEM_2
POS_3
VCC
PH_2
VCC
PH_3
Current sharing groups require proper synchronization prior to
ramp events. Resistor pin-strap the SS pin to set the following
parameters:
a. Delay Time – The reference device’s soft-start delay time
must be at least 10ms greater than any member device to
ramp up/down current sharing. The reference device requires
this additional time to coordinate a synchronization signal to
all member devices.
b. Ramp Time – A minimum soft-start ramp time of 5ms is
required for both reference and member devices to ramp
up/down current sharing.
Phase Enable (PH_EN Pin)
SYNC_In
FIGURE 24. 3-phase Current Sharing Group
SMBus Address (SA0, SA1 Pins)
Assign sequential SMBus addresses to each device in the current
sharing group. If other non-current sharing devices are connected
to the same SMBus then assign addresses to these devices that
are before or after the current sharing group.
Current Share Pin-Straps (CFG0, CFG2 Pins)
Resistor pin-strap the CFG0 pin to set the following parameters:
a. Current Share # of Members – Number of devices or phases
in a current sharing group (2 minimum and 8 maximum).
b. Current Share Control – Current sharing is automatically
enabled when the number of members is 2 (and disabled
when members is = 0).
Resistor pin-strap the CFG2 pin to set the current share position:
c. Current Share Position – Sequential numbering from 0 to 7
(max) of N number of members starting with the reference
device in position 0 and ending with the last member device
in position N-1.
For the 3-phase group the parameters for each device are shown
in Table 32.
TABLE 32. Current Share Parameters
Phase enable is used to dynamically add or drop a current
sharing phase during operation. Set the PH_EN pin high to
enable a phase and low to disable a phase (open is an invalid
state). The PH_EN pin replaces the PHASE_CONTROL command.
For proper operation, the pin must be externally driven high or
low without switching glitches. Also, ensure phase enable is high
for the reference and member devices of a current sharing group
prior to ramp-up.
MFR_CONFIG Command
Application specific values are set by the MFR_CONFIG
command. The following parameters must be set to properly
configure current sharing.
a. Current Sense Blanking Delay (bits 15:11) – The current
sense delay parameter controls the blanking time when no
current measurement is taken. This allows the filtering of
noise from the current measurement circuit when the FETs
are switching. The actual value selected depends on f SW ,
sensing method and ring-out duration. The same delay is
used for both reference and member devices.
b. Current Sense Control (bits 5:4) – Three modes of current
sensing are available depending on duty cycle and switching
for both reference and member devices.
Device
Reference
Member_1
Member_2
SMBus Address
0x20
0x21
0x22
# of Members
3
3
3
Position
0
1
2
Control
Enabled
Enabled
Enabled
36
FN6859.4
April 29, 2011
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相关代理商/技术参数 |
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| ZL2008ALAFT1 | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
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