参数资料
型号: ZL2008ALAFT
厂商: Intersil
文件页数: 19/42页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 36-QFN
标准包装: 100
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 95%
电源电压: 3 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL2008
Now the output inductance can be calculated using Equation 5,
shown in Equations 9 and 10:
V OUT × ? ? 1 ? OUT
? ?
?
?
V INM
where V INM is the maximum input voltage:
? V ?
(EQ. 5)
L OUT =
fsw × I opp
The average inductor current is equal to the maximum output
current. The peak inductor current (I Lpk ) is calculated using
Equation 6 where I OUT is the maximum output current:
C OUT =
ESR =
I opp
8 × f sw ×
V orip
2 × I opp
V orip
2
(EQ. 9)
(EQ. 10)
I Lpk = I OUT +
I opp
2
(EQ. 6)
Use these values to make an initial capacitor selection, using a
single capacitor or several capacitors in parallel.
After a capacitor has been selected, the resulting output voltage
Select an inductor rated for the average DC current with a peak
ripple can be calculated using Equation 11:
current rating above the peak current computed above.
In overcurrent or short-circuit conditions, the inductor may have
currents greater than 2X the normal maximum rated output
V orip = I opp × ESR +
I opp
8 × f sw × C OUT
(EQ. 11)
current. It is desirable to use an inductor that still provides some
P LDCR = DCR × I Lrms
(EQ. 7)
( I )
I Lrms = I OUT +
I CINrms = I OUT × D × ( 1 ? D )
inductance to protect the load and the MOSFETs from damaging
currents in this situation.
Once an inductor is selected, the DCR and core losses in the
inductor are calculated. Use the DCR specified in the inductor
manufacturer’s datasheet.
2
I Lrms is given by Equation 8:
2
2 opp (EQ. 8)
12
where I OUT is the maximum output current. Next, calculate the
core loss of the selected inductor. Since this calculation is
specific to each inductor and manufacturer, refer to the chosen
inductor datasheet. Add the core loss and the ESR loss and
compare the total loss to the maximum power dissipation
recommendation in the inductor datasheet.
OUTPUT CAPACITOR SELECTION
Several trade-offs must also be considered when selecting an
output capacitor. Low ESR values are needed to have a small
output deviation during transient load steps (V osag ) and low
output voltage ripple (V orip ). However, capacitors with low ESR,
such as semi-stable (X5R and X7R) dielectric ceramic capacitors,
also have relatively low capacitance values. Many designs can
use a combination of high capacitance devices and low ESR
devices in parallel.
For high ripple currents, a low capacitance value can cause a
significant amount of output voltage ripple. Likewise, in high
transient load steps, a relatively large amount of capacitance is
needed to minimize the output voltage deviation while the
inductor current ramps up or down to the new steady state
output current value.
As a starting point, apportion one-half of the output ripple
voltage to the capacitor ESR and the other half to capacitance, as
19
Because each part of this equation was made to be less than or
equal to half of the allowed output ripple voltage, the V orip should
be less than the desired maximum output ripple.
INPUT CAPACITOR
It is highly recommended that dedicated input capacitors be
used in any point-of-load design, even when the supply is
powered from a heavily filtered 5V or 12V “bulk” supply from an
off-line power supply. This is because of the high RMS ripple
current that is drawn by the buck converter topology. This ripple
(I CINrms ) can be determined from Equation 12:
(EQ. 12)
Without capacitive filtering near the power supply circuit, this
current would flow through the supply bus and return planes,
coupling noise into other system circuitry. The input capacitors
should be rated at 1.2X the ripple current calculated above to
avoid overheating of the capacitors due to the high ripple current,
which can cause premature failure. Ceramic capacitors with X7R
or X5R dielectric with low ESR and 1.1X the maximum expected
input voltage are recommended.
BOOTSTRAP CAPACITOR SELECTION
The high-side driver boost circuit utilizes an external Schottky
diode (D B ) and an external bootstrap capacitor (C B ) to supply
sufficient gate drive for the high-side MOSFET driver. D B should
be a 20mA, 30V Schottky diode or equivalent device and C B
should be a 1μF ceramic type rated for at least 6.3V.
QL SELECTION
The bottom MOSFET should be selected primarily based on the
device’s R DS(ON) and secondarily based on its gate charge. To
choose QL, use the following equation and allow 2% to 5% of the
output power to be dissipated in the R DS(ON) of QL (lower output
voltages and higher step-down ratios will be closer to 5%):
FN6859.4
April 29, 2011
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