参数资料
型号: ZL2008ALAFT
厂商: Intersil
文件页数: 17/42页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 36-QFN
标准包装: 100
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 95%
电源电压: 3 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL2008
Switching Frequency and PLL
The ZL2008 incorporates an internal phase-locked loop (PLL) to
clock the internal circuitry. The PLL can be driven by an external
clock source connected to the SYNC pin. When using the internal
oscillator, the SYNC pin can be configured as a clock source for
other Zilker Labs devices.
The SYNC pin is a unique pin that can perform multiple functions
depending on how it is configured. The CFG1 pin is used to select
the operating mode of the SYNC pin as shown in Table 9.
Figure 14 illustrates the typical connections for each mode.
TABLE 9. SYNC Pin Function Selection
clock signal must also exhibit the necessary performance
requirements (see “Electrical Specifications” on page 4). In the
event of a loss of the external clock signal, the output voltage
may show transient over/undershoot.
If this happens, the ZL2008 will automatically switch to its
internal oscillator and switch at a frequency close to the previous
incoming frequency.
Configuration C: SYNC AUTO DETECT
When the SYNC pin is configured in auto detect mode (CFG1 pin
is left OPEN), the device will automatically check for a clock
signal on the SYNC pin after enable is asserted.
CFG1 Pin
LOW
OPEN
HIGH
SYNC Pin Function
SYNC is configured as an input
Auto Detect mode
SYNC is configured as an output
f SW = 400kHz
If a clock signal is present, The ZL2008’s oscillator will then
synchronize the rising edge of the external clock. Refer to SYNC
INPUT description.
If no incoming clock signal is present, the ZL2008 will configure
the switching frequency according to the state of the SYNC pin as
listed in Table 10. In this mode, the ZL2008 will only read the
Configuration A: SYNC OUTPUT
When the SYNC pin is configured as an output (CFG1 pin is tied
HIGH), the device will run from its internal oscillator and will drive the
resulting internal oscillator signal (preset to 400kHz) onto the SYNC
SYNC pin connection during the start-up sequence. Changes to
SYNC pin connections will not affect f SW until the power (VDD) is
cycled off and on.
TABLE 10. Switching Frequency Pin-strap Setting
pin so other devices can be synchronized to it. The SYNC pin will not
be checked for an incoming clock signal while in this mode.
Configuration B: SYNC INPUT
When the SYNC pin is configured as an input (CFG1 pin is tied
LOW), the device will automatically check for a clock signal on
the SYNC pin each time EN is asserted. The ZL2008’s oscillator
SYNC Pin
LOW
OPEN
HIGH
Resistor
Frequency
200kHz
400kHz
1MHz
See Table 11
will then synchronize with the rising edge of the external clock.
The incoming clock signal must be in the range of 200kHz to
1.4MHz and must be stable when the enable pin is asserted. The
Logic
high
SYNC
If the user wishes to run the ZL2008 at a frequency not listed in
Table 10, the switching frequency can be set using an external
resistor, R SYNC , connected between SYNC and SGND using Table 11.
SYNC
200 kHz – 1.33MHz
N/ C
ZL
A) SYNC = output
Logic
200kHz – 1.4MHz
N/ C
ZL
B) SYNC = input
N/C
high
SYNC
Open
SYNC
SYNC
200kHz – 1.4MHz
ZL
OR
Logic
ZL
OR
R SYNC
ZL
low
C) SYNC = Auto Detect
FIGURE 14. Sync Pin Configurations
17
FN6859.4
April 29, 2011
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