参数资料
型号: ZL2008ALAFT
厂商: Intersil
文件页数: 12/42页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 36-QFN
标准包装: 100
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 95%
电源电压: 3 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL2008
Multi-mode Pins
In order to simplify circuit design, the ZL2008 incorporates
patented multi-mode pins that allow the user to easily configure
many aspects of the device with no programming. Most power
management features can be configured using these pins. The
multi-mode pins can respond to four different connections as
shown in Table 1. These pins are sampled when power is applied
or by issuing a PMBus Restore command (See Application Note
AN2033).
Pin-strap Settings: This is the simplest implementation method,
as no external components are required. Using this method, each
pin can take on one of three possible states: LOW, OPEN, or
HIGH. These pins can be connected to the V25 pin for logic HIGH
settings as this pin provides a regulated voltage higher than 2V.
Using a single pin, one of three settings can be selected. Using
two pins, one of nine settings can be selected.
TABLE 1. Multi-mode Pin Configuration
Pin Tied To Value
LOW < 0.8VDC
(Logic LOW)
The SMBus device address and VOUT_MAX are the only
parameters that must be set by external pins. All other device
parameters can be set via the I 2 C/SMBus. The device address is
set using the SA0 and SA1 pins. VOUT_MAX is determined as
10% greater than the voltage set by the V0 and V1 pins.
Power Conversion Functional
Description
Internal Bias Regulators and Input Supply
Connections
The ZL2008 employs two internal low dropout (LDO) regulators to
supply bias voltages for internal circuitry, allowing it to operate
from a single input supply. The internal bias regulators are as
follows:
VR: The VR LDO provides a regulated 5V bias supply for the
MOSFET driver circuits. It is powered from the VDD pin. A 4.7μF
filter capacitor is required at the VR pin.
V25: The V25 LDO provides a regulated 2.5V bias supply for the
main controller circuitry. It is powered from an internal 5V node.
A 10μF filter capacitor is required at the V25 pin.
OPEN
(N/C)
HIGH
(Logic HIGH)
Resistor to SGND
No connection
> 2.0VDC
Set by resistor value
When the input supply (VDD) is higher than 5.5V, the VR pin
should not be connected to any other pins. It should only have a
filter capacitor attached as shown in Figure 8. Due to the dropout
voltage associated with the VR bias regulator, the VDD pin must
be connected to the VR pin for designs operating from a supply
below 5.5V. Figure 8 illustrates the required connections for both
cases.
V IN
V IN
Logic
high
Open
ZL
Multi- mode Pin
ZL
Multi- mode Pin
ZL
VDD
VR
ZL
VDD
VR
R SET
Logic
low
Pin-strap
Settings
Resistor
Settings
3V ≤ V IN ≤ 5.5V 5.5V <V IN ≤ 14V
FIGURE 8. Input Supply Connections
FIGURE 7. Pin-strap and Resistor Setting Examples
Resistor Settings: This method allows a greater range of
adjustability when connecting a finite value resistor (in a
specified range) between the multi-mode pin and SGND.
Standard 1% resistor values are used, and only every fourth E96
resistor value is used so the device can reliably recognize the
value of resistance connected to the pin while eliminating the
error associated with the resistor accuracy. Up to 31 unique
selections are available using a single resistor.
I 2 C/SMBus Method: Almost any ZL2008 function can be
configured via the I 2 C/SMBus interface using standard PMBus
commands. Additionally, any value that has been configured
using the pin-strap or resistor setting methods can also be
re-configured and/or verified via the I 2 C/SMBus. See Application
Note AN2033 for more details.
12
Note: the internal bias regulators are not designed to be outputs
for powering other circuitry. Do not attach external loads to any of
these pins. The multi-mode pins may be connected to the V25
pin for logic HIGH settings.
High-side Driver Boost Circuit
The gate drive voltage for the high-side MOSFET driver is
generated by a floating bootstrap capacitor, CB (see Figure 5).
When the lower MOSFET (QL) is turned on, the SW node is pulled
to ground and the capacitor is charged from the internal VR bias
regulator through diode DB. When QL turns off and the upper
MOSFET (QH) turns on, the SW node is pulled up to V DD and the
voltage on the bootstrap capacitor is boosted approximately 5V
above V DD to provide the necessary voltage to power the
high-side driver. A Schottky diode should be used for DB to help
maximize the high-side drive supply voltage.
FN6859.4
April 29, 2011
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