参数资料
型号: ZL2008ALAFT
厂商: Intersil
文件页数: 22/42页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 36-QFN
标准包装: 100
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 95%
电源电压: 3 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL2008
TABLE 15. Current Limit Threshold Voltage Resistor Settings
V IN
R LIM
(k Ω )
10
11
12.1
13.3
R DS V LIM
(mV)
0
5
10
15
DCR V LIM
(mV)
0
2.5
5
7.5
DPWM
D
1-D
L
C
R C
R O
V OUT
14.7
20
10
16.2
17.8
19.6
21.5
23.7
26.1
28.7
31.6
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
75
82.5
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
12.5
15
17.5
20
22.5
25
27.5
30
32.5
35
37.5
40
42.5
45
47.5
50
52.5
55
Compensation
FIGURE 17. Control Loop Block Diagram
In the ZL2008, the compensation zeros and gain are set by
configuring the FC0 and FC1 pins or via the I 2 C/SMBus interface
once the user has calculated the required settings. This method
eliminates the inaccuracies due to the component tolerances
associated with using external resistors and capacitors required
with traditional analog controllers.
The compensation is configured using a baseline set of PID taps
which are scaled on the factors of Gain, Q and Fn as shown in
Tables 16, 17 and 18. The parameters Gain, Q and Fn are defined
in AN2035 and are parameters of the compensator (not the
power stage being compensated).
The selection of these scaling factors is based on compensation
required for additional output capacitance used in an
application.
TABLE 16. FC0 Pin-strap Settings
FC0 Pin Gain Scale (dB) Q-new/Q-base
90.9
115
57.5
LOW
-12
100
120
60
OPEN
0
1
The threshold voltage can also be selected in 5mV increments by
HIGH
6
connecting a resistor, R LIM , between the ILIM pin and ground
according to Table 15. This method is preferred if the user does not
desire to use or does not have access to the I 2 C/SMBus interface
and the desired threshold value is contained in Table 15.
TABLE 17. FC1 Pin-strap Settings
FC1 Pin Fn-new/Fn-base
LOW
The current limit threshold can also be set to a custom value via
the I 2 C/SMBus interface. Please refer to Application Note
AN2033 for further details.
OPEN
HIGH
1
Loop Compensation
The ZL2008 operates as a voltage-mode synchronous buck
controller with a fixed frequency PWM scheme. Although the
The scaling factors are applied to the baseline set of taps to
achieve the desired compensation results. These baseline taps
correspond to zeroes of the form:
+ ? ?
? ?
ZL2008 uses a digital control loop, it operates much like a
traditional analog PWM controller. Figure 17 is a simplified block
diagram of the ZL2008 control loop, which differs from an
analog control loop only by the constants in the PWM and
?
G base ? 1 +
?
s ? s ? 2 ?
( Q base ? 2 π f n base ) ? ( Q base * 2 π f n base ) ? ? ?
(EQ. 31)
compensation blocks. As in the analog controller case, the
compensation block compares the output voltage to the desired
voltage reference and compensation zeroes are added to keep
the loop stable. The resulting integrated error signal is used to
drive the PWM logic, converting the error signal to a duty cycle to
drive the external MOSFETs.
22
Where G base = 20dB
Q base = 2
f nbase = f SW /10
Both the baseline taps and the calculated taps determined by the
FC0 and FC1 resistors can be read via the I 2 C/SMBus interface.
Please refer to Application Note AN2033 for further details.
FN6859.4
April 29, 2011
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