Rev.2.00
REJ03B0202-0200
Mar 05, 2007
Page 21 of 70
7549 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 8
Interrupt vector address and priority
NOTES:
1. Vector addressed contain internal jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
Interrupt source
Priority
Vector addresses
(Note 1)
High-
order
FFFD
16
FFFB
16
FFF9
16
Interrupt request generating conditions
Remarks
Low-
order
FFFC
16
FFFA
16
FFF8
16
Reset (Note 2)
Serial I/O receive
Serial I/O transmit
1
2
3
At reset input
At completion of serial I/O data receive
At completion of serial I/O transmit shift or
when transmit buffer is empty
At detection of either rising or falling edge
of INT
0
input
At detection of either rising or falling edge
of INT
1
input
At falling of conjunction of input logical
level for port P1 (at input)
At detection of either rising or falling edge
of Capture 0 input
At compare matched
At timer A underflow
At timer 2 underflow
At completion of A/D conversion
At timer 1 underflow
Non-maskable
Valid only when serial I/O is selected
Valid only when serial I/O is selected
INT
0
4
FFF7
16
FFF6
16
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling edge)
INT
1
5
FFF5
16
FFF4
16
Key-on wakeup
6
FFF3
16
FFF2
16
Capture
7
FFF1
16
FFF0
16
External interrupt
(active edge selectable)
Compare interrupt source is selected.
Compare
Timer A
Timer
2
A/D conversion
Timer
1
Not used
8
9
10
11
12
13
14
15
16
17
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
STP release timer underflow
BRK instruction
At BRK instruction execution
Non-maskable software interrupt