Rev.2.00
REJ03B0202-0200
Mar 05, 2007
Page 45 of 70
7549 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Oscillation Control
Clock mode register
Clock mode register contains the oscillation control bits of each
oscillation circuits, clock selection bits and etc
Clock selection bits
φ
SOURCE can be selected by the clock selection bits (bits 5 and
4 in clock mode register).
φ
SOURCE can be selected from low-
speed on-chip oscillator, high-speed on-chip oscillator, X
IN
/X
CIN
oscillaton or external clock input by the clock selection bits.
φ
SOURCE is also used to the clock for peripheral functions.
When the oscillation method selection bits (bits 1 and 0 in
FSROM1) is set to “00
2
” (oscillation pins not used), setting the
clock selection bits to “10
2
” (X
IN
/X
CIN
oscillation, external
clock input) is disabled.
Clock division ratio selection bit
The internal clock
φ
is generated by dividing
φ
SOURCE.
Select the division ratio using the clock division ration selection
bits (bits 7 and 6 in CLKM).
The division ratio can be selected from among
φ
SOURCE/8
(low-speed mode), /4 (middle-speed mode), /2 (high-speed
mode), and no division (double-speed mode).
Table 9 shows the division ratio (mode) settings.
When releasing reset, the low-speed on-chip oscillator is selected
as
φ
SOURCE, and
φ
SOURCE/8 is selected as the internal clock.
The high-speed on-chip oscillator is stopped at this time. If an
oscillation circuit is connected to the clock pin, oscillation starts.
To switch
φ
SOURCE to X
IN
/X
CIN
oscillation, generate wait time
using the on-chip oscillator until the oscillation is stabilized.
: can be “0” or “1”, no change in outcome
Table 9
Setting the clock division (mode)
φ
SOURCE
CLKM
Clock division
ratio selection
bits
Bit 7, 6
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
FSROM1
Oscillation
method
selection bits
Bit 1, 0
01
01
01
01
10
10
10
10
11
11
11
11
FSROM2
Low-speed on-
chip oscillator
control bit
Bit 4
1/0
1/0
1/0
1/0
Clock
selection bits
X
IN
/XC
IN
oscillation
control bit
Bit 2
0
0
0
0
0
0
0
0
High-speed on-chip
oscillator oscillation
control bit
Bit 1
0
0
0
0
Low-speed on-chip
oscillator oscillation
control bit
Bit 0
0
0
0
0
Bit 5, 4
10
10
10
10
10
10
10
10
10
10
10
10
01
01
01
01
00
00
00
00
X
IN
Double-speed
High-speed
Middle-speed
Low-speed
Double-speed
High-speed
Middle-speed
Low-speed
Double-speed
High-speed
Middle-speed
Low-speed
Double-speed
High-speed
Middle-speed
Low-speed
Double-speed
High-speed
Middle-speed
Low-speed
X
CIN
External
clock
High-speed
on-chip
oscillator
Low-speed
on-chip
oscillator
bit
Mode