Rev.2.00
REJ03B0202-0200
Mar 05, 2007
Page 34 of 70
7549 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but
the two buffers have the same address in memory. Since the shift
register cannot be written to or read from directly, transmit data
is written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig 44. Block diagram of UART serial I/O
Fig 45. Operation of UART serial I/O function
1/4
OE
PE
FE
1/16
1/16
Data bus
Data bus
Receive buffer register
Address 0018
16
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Address 001C
16
Frequency division ratio 1/(n+1)
ST/SP/PA generator
Transmit buffer register
Transmit shift register
Address 0018
16
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address 0019
16
ST detector
SP detector
UART control register
Address 001B
16
Character length selection bit
Address 001A
16
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O1 synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O1 status register
Serial I/O 1 control register
P0
6
/S
CLK
P0
4
/R
X
D
P0
5
/T
X
D
φ
SOURCE
TBE=1
RBF=0
TBTSC=0
TBE=0
RBF=1
RBF=1
TBE=1
TSC=1*
ST
D
0
D
1
SP
D
0
D
1
ST
SP
Transmit or receive clock
Trawrite signal
Serial output T
X
D
Receive buffer
read signal
Serial input R
X
D
* Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
ST
D
0
D
1
SP
D
0
D
1
ST
SP