参数资料
型号: 7549
厂商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 单芯片8位CMOS微机
文件页数: 31/73页
文件大小: 1272K
代理商: 7549
Rev.2.00
REJ03B0202-0200
Mar 05, 2007
Page 31 of 70
7549 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Input capture
7549 group has 1-input capture channel and can be used to
capture count value of Timer A.
Input capture shares the registers with three output capture
channels, but their individual circuits operate independently so
that all the channels can be used at the same time.
To use input capture, set the input capture port selection bits. If
P0
3
is selected, set the P0
3
direction register to 0. When an input
capture trigger is input to the input capture circuit, the count
value of timer A is saved to the capture latches. The timer count
value at the rising edge of the external input trigger is saved to
capture latch 00, and the timer count value at the falling edge of
the external input trigger is saved to capture latch 01. Capture
latch 00 and capture latch 01 can be read using the following
procedure.
1.Set the capture/compare register R/W pointer to the read
target address.
2.Read the high-order bits of the capture/compare registers,
then read the low-order bits of the capture/compare regis-
ters. (Read both the capture/compare registers in the
sequence of high-order bits followed by low-order bits.)
The count value of timer can be retained by software by capture
y (y = 00, 01, 10, 11) software trigger bit too. When “1” is set to
this bit, count value of timer is retained to the corresponded
capture latch.
When reading from the capture y software trigger bit is executed,
“0” is read out.
Notes on Input Capture
When the low-speed on-chip oscillator output or X
CIN
input
clock is selected as the count source of timer A, input capture
can be used only if the same clock source is selected as
φ
SOURCE and as the count source of timer A.
When writing “1” to capture y software trigger bit of capture
latch 00 and 01 at the same time, or external trigger and
software trigger occur simultaneously, if capture latches 00
and 01 are input simultaneously, the set value of capture 0
status bit is undefined.
When setting the interrupt active edge selection bit and noise
filter clock selection bit of captupe 0 the interrupt request bit
may be set to “1”.
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
(1) Set the capture interrupt enable bit to “0” (disabled).
(2) Set the interrupt edge selection bit or noise filter clock
selection bit.
(3) Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
(4) Set the capture interrupt enable bit to “1” (enabled).
When the capture interrupt is used as the interrupt for return
from stop mode, set the capture 0 noise filter clock selection
bits to “00 (Filter stop)”.
Fig 37. Structure of capture software trigger register
Fig 38. Structure of capture mode register
b7
b0
Capture software trigger register
16
, initial value: 00
16
)
CaCapture 00 software trigger occurs by setting “1”
to this bit. (returns “0” when read)
CaCapture 01 software trigger occurs by setting “1”
to this bit. (returns “0” when read)
Not used (returns “0” when read)
b7
b0
Cab1 b0
0 0 : Rising and falling edge
Cab1 b0
IN
IN
0 0 : Filter)
IN
)/8
Not used (returns “0” when read)
Capture mode register
16
, initial value: 00
16
)
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