Rev.2.00
REJ03B0202-0200
Mar 05, 2007
Page 25 of 70
7549 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig 22. Structure of timer mode register
Fig 23. Structure of timer count source set register
Fig 24. Block diagram of timer 1 and timer 2
b7
b0
Timer mode register
(TM: address 002B
16
, initial value: 00
16
)
Not used (return “0” when read)
Timer 2 count stop bit
0: Count start
1: Count stop
P1
3
/T2
OUT
output valid bit
0: Pulse output invalid (I/O port)
1: Pulse output valid
T2
OUT
polarity selection bit
0: Start from “H” level
1: Start from “L” level
Timer 2 write control bit
0: Write to latch and timer simultaneously
1: Write to only latch
Timer A write control bit
0: Write to latch and timer simultaneously
1: Write to only latch
Timer A count stop bit
0: Count start
1: Count stop
Not used (return “0” when read)
b7
b0
Timer count source set register
(TCSS: address 002C
16
, initial value: 00
16
)
Timerb1 b0
φ
φ
SOURCE/16
0 0 :
Timerb4 b3 b2
φ
φ
φ
φ
φ
φ
SOURCE/16
0 0 (32kHz quartz crystal oscillation)
CIN
input clock
Prescaler 12 count source selection bit
SO input clock
CIN
0 :
Not used (return “0” when read)
Note 1:
φ
16
).
rSOURCE is the clock selected by bits 5 and 4 in the clock mode register (0037
Data bus
Timer 1
interrupt
request
φ
SOURCE/16
X
CIN
input clock
(32kHz quartz
crystal oscillation)
Data bus
Prescaler 12 latch (8)
Timer 1 latch (8)
Prescaler 12 (8)
Timer 1 (8)
φ
SOURCE/256
φ
SOURCE/16
Timer 2 count
stop bit
Timer 2 count
source selection bit
Prescaler 12 count
source selection bit
Timer 2
interrupt
request
Timer 2 latch (8)
Timer 2 (8)
Timer A underflow
Timer 2 write
control bit
Toggle flip-flop
T
Q
Q
P1
3
/T2
OUT
output valid bit
R
T2
OUT
polarity
selection bit
“1”
“0”
P1
3
/T2
OUT
output valid bit
Port P1
3
latch
Port P1
3
direction
register
P1
3
/T2
OUT