Rev.2.00
REJ03B0202-0200
Mar 05, 2007
Page 46 of 70
7549 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Stop mode
When the STP instruction is executed, the internal clock
φ
stops
at an “H” level and the X
IN
/X
CIN
and on-chip oscillator stops. At
this time, timer 1 is set to “01
16
” and prescaler 12 is set to “FF
16
”
when the oscillation stabilization time set bit after release of the
STP instruction is “0”. On the other hand, timer 1 and prescaler
12 are not set when the above bit is “1”. Accordingly, set the wait
time fit for the oscillation stabilization time of the oscillator to be
used. When an external interrupt is accepted, oscillation is
restarted but the internal clock
φ
remains at “H” until timer 1
underflows. As soon as timer 1 underflows, the internal clock
φ
is supplied. This is because when a ceramic resonator is used,
some time is required until a start of oscillation. In case
oscillation is restarted by reset, no wait time is generated. So
apply an “L” level to the RESET pin while oscillation becomes
stable, or set the wait time by on-chip oscillator operation after
system is released from reset until the oscillation is stabled.
Wait mode
If the WIT instruction is executed, the internal clock
φ
stops at an
“H” level, but the oscillator does not stop. The internal clock
restarts if a reset occurs or when an interrupt is received. Since
the oscillator does not stop, normal operation can be started
immediately after the clock is restarted. To ensure that interrupts
will be received to release the STP or WIT state, interrupt enable
bits must be set to “1” before the STP or WIT instruction is
executed.
Note on Oscillation Control
For use with the oscillation stabilization set bit after release of
the STP instruction set to “1”, set values in timer 1 and prescaler
12 after fully appreciating the oscillation stabilization time of the
oscillator to be used.