Rev.2.00
REJ03B0202-0200
Mar 05, 2007
Page 22 of 70
7549 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig 19. Interrupt control
Fig 20. Structure of Interrupt-related registers
Interrupt disable flag I
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
b7
b0
INT
0
0: Falling edge active
1: Rising edge active
INT
1
0: Falling edge active
1: Rising edge active
Not used (returns “0” when read)
Interrupt edge selection register
16
, initial value: 00
16
)
b7
b0
Interrupt request register 1
16
, initial value: 00
16
)
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
INT
0
interrupt request bit
INT
1
interrupt request bit
Key-on wake up interrupt request bit
Capture interrupt request bit
Compare interrupt request bit
Timer A interrupt request bit
0: No interrupt request issued
b7
b0
b7
b0
b7
b0
Interrupt request register 2
16
, initial value: 00
16
)
Timer 2 interrupt request bit
A/D conversion interrupt request bit
Timer 1 interrupt request bit
Not used (returns “0” when read)
0: No interrupt request issued
1: Interrupt request issued
Interrupt control register 1
16
, initial value: 00
16
)
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
INT
0
interrupt enable bit
INT
1
interrupt enable bit
Key-on wake up interrupt enable bit
Capture interrupt enable bit
Compare interrupt enable bit
Timer A interrupt enable bit
0: Interrupts disabled
1: Interrupts enabled
Interrupt control register 2
16
, initial value: 00
16
)
Timer 2 interrupt enable bit
A/D conversion interrupt enable bit
Timer 1 interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0: Interrupts disabled
1: Interrupts enabled