参数资料
| 型号： | AD9852ASVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/52页 |
| 文件大小： | 0K |
| 描述： | IC DDS SYNTHESIZER CMOS 80-TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 12 b |
| 主 fclk： | 300MHz |
| 调节字宽（位）： | 48 b |
| 电源电压： | 3.14 V ~ 3.47 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-TQFP 裸露焊盘 |
| 供应商设备封装： | 80-TQFP-EP（12x12） |
| 包装： | 托盘 |
| 配用： | AD9852/PCBZ-ND - BOARD EVAL FOR AD9852 |
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AD9852
Rev. E | Page 22 of 52
Additional flexibility in the ramped FSK mode is provided by
the AD9852’s ability to respond to changes in the 48-bit delta
frequency word and/or the 20-bit ramp rate counter at any time
during the ramping from F1 to F2 or vice versa. To create these
nonlinear frequency changes, it is necessary to combine several
linear ramps with different slopes in a piecewise fashion. This is
done by programming and executing a linear ramp at a rate or
slope and then altering the slope (by changing the ramp rate
clock or delta frequency word, or both). Changes in slope can
be made as often as needed before the destination frequency has
been reached to form the desired nonlinear frequency sweep
response. These piecewise changes can be precisely timed using
the 32-bit internal update clock (see the Internal and External
Update Clock section).
Nonlinear ramped FSK has the appearance of the chirp function
shown in Figure 41. The major difference between a ramped
FSK function and a chirp function is that FSK is limited to
operation between F1 and F2, whereas chirp operation has no
F2 limit frequency.
Two additional control bits (CLR ACC1 and CLR ACC2) are
available in the ramped FSK mode that allow more options. Setting
CLR ACC1 (Register Address 1F hex) high clears the 48-bit
frequency accumulator (ACC1) output with a retriggerable
one-shot pulse of one system clock duration. If the CLR ACC1
bit is left high, a one-shot pulse is delivered on the rising edge of
every update clock. The effect is to interrupt the current ramp,
reset the frequency to the start point (F1 or F2), and then
continue to ramp up (or down) at the previous rate. This occurs
even when a static F1 or F2 destination frequency has been
achieved.
Alternatively, the CLR ACC2 control bit (Register Address 1F hex)
can be used to clear both the frequency accumulator (ACC1)
and the phase accumulator (ACC2). When this bit is set high,
the output of the phase accumulator results in 0 Hz output from
the DDS. As long as this bit is set high, the frequency and phase
accumulators are cleared, resulting in 0 Hz output. To return to
previous DDS operation, CLR ACC2 must be set to logic low.
CHIRP (MODE 011)
Chirp mode is also known as pulsed FM. Most chirp systems
use a linear FM sweep pattern, but the AD9852 can also support
nonlinear patterns. In radar applications, use of chirp or pulsed
FM allows operators to significantly reduce the output power
needed to achieve the same result a single frequency radar
system produces. Figure 41 represents a very low resolution
nonlinear chirp that demonstrates the different slopes created
by varying the time steps (ramp rate) and frequency steps (delta
frequency word).
The AD9852 permits precise, internally generated linear,
or externally programmed nonlinear, pulsed or continuous
FM over the complete frequency range, duration, frequency
resolution, and sweep direction(s). All of these options are user
programmable. A block diagram of the FM chirp components
is shown in Figure 40.
F1
F2
0
FREQUENCY
MODE
TW1
TW2
FSK DATA
F1
F2
000 (DEFAULT)
0
010 (RAMPED FSK)
I/O UD CLK
00634-039
Figure 39. Effect of Premature Ramped FSK Data
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9852ASVZ | 制造商:Analog Devices 功能描述:IC DDS 300MHz TQFP-80 制造商:Analog Devices 功能描述:IC, DDS, 300MHz, TQFP-80 |
| AD9852ASVZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS |
| AD9852BSVZ | 制造商:Analog Devices 功能描述: |
| AD9853 | 制造商:AD 制造商全称:Analog Devices 功能描述:Programmable Digital OPSK/16-QAM Modulator |
| AD9853-45PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Programmable Digital OPSK/16-QAM Modulator |
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