参数资料
| 型号： | AD9852ASVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/52页 |
| 文件大小： | 0K |
| 描述： | IC DDS SYNTHESIZER CMOS 80-TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 12 b |
| 主 fclk： | 300MHz |
| 调节字宽（位）： | 48 b |
| 电源电压： | 3.14 V ~ 3.47 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-TQFP 裸露焊盘 |
| 供应商设备封装： | 80-TQFP-EP（12x12） |
| 包装： | 托盘 |
| 配用： | AD9852/PCBZ-ND - BOARD EVAL FOR AD9852 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页当前第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页
AD9852
Rev. E | Page 42 of 52
Programming
If a PC and Analog Devices software are not used to program
the AD9852, the W9, W11, W12, W13, W14, and W15 headers
should be opened (shorting jumpers removed). This effectively
detaches the PC interface and allows J10 (the 40-pin header) and J1
to assume control without bus contention. Input signals on J10
and J1 going to the AD9852 should be 3.3 V CMOS logic levels.
Low-Pass Filter Testing
The purpose of the 2-pin W7 and W10 headers (associated with
J4 and J5) is to allow the two 50 Ω, 120 MHz filters to be tested
during PCB assembly without interference from other circuitry
attached to the filter inputs. Normally, a shorting jumper is attached
to each header to allow the DAC signals to be routed to the filters.
If the user wishes to test the filters, the shorting jumpers at W7 and
W10 should be removed and 50 Ω test signals should be applied at
the J4 and J5 inputs to the 50 Ω elliptic filters. The user can refer to
the provided schematic (Figure 61 and Figure 62) and the
following sections to properly position the remaining shorting
jumpers.
Observing the Unfiltered IOUT1 and the Unfiltered
IOUT2 DAC Signals
The unfiltered DAC outputs can be observed at J5 (the I, or
cosine DAC, signal) and J4 (the Q, or control DAC, signal). Use
the following procedure to route the two 50 Ω terminated analog
DAC outputs to the SMB connectors and to disconnect any other
circuitry.
1.
Install shorting jumpers at W7 and W10.
2.
Remove the shorting jumper at W16.
3.
Remove the shorting jumper from the 3-pin W1 header.
4.
Install a shorting jumper on Pin 1 and Pin 2 (bottom two
pins) of the 3-pin W4 header.
The raw DAC outputs may appear as a series of quantized
(stepped) output levels that do not resemble a sine wave until
they are filtered. The default 10 mA output current develops a
0.5 V p-p signal across the on-board 50 Ω termination. If the
observation equipment uses 50 Ω inputs, the DAC develops
only 0.25 V p-p due to the double termination.
If using the AD9852 evaluation board, the user can control
IOUT2 (the control DAC output) by using the serial or parallel
ports. The 12-bit, twos complement value(s) is/are written to
the control DAC register that sets the IOUT2 output to a static
dc level. Allowable hexadecimal values are 7FF (maximum) to
800 (minimum), with all 0s being midscale. Rapidly changing
the contents of the control DAC register (up to 100 MSPS)
allows IOUT2 to assume any programmable waveform.
Observing the Filtered IOUT1 and the Filtered IOUT2
The filtered I (cosine DAC) and Q (control DAC) outputs can
be observed at J6 (the I, or cosine DAC, signal) and J7 (the Q, or
control DAC, signal). Use the following procedure to route the
50 Ω (input and output Z) low-pass filters into the pathways of
the I and Q signals to remove images, aliased harmonics, and
other spurious signals that are greater than approximately
120 MHz:
1.
Install shorting jumpers at W7 and W10.
2.
Install a shorting jumper at W16.
3.
Install a shorting jumper on Pin 1 and Pin 2 (bottom two pins)
of the 3-pin W1 header.
4.
Install a shorting jumper on Pin 1 and Pin 2 (bottom two pins)
of the 3-pin W4 header.
5.
Install a shorting jumper on Pin 2 and Pin 3 (bottom two pins)
of the 3-pin W2 and W8 headers.
The resulting signals appear as nearly pure sine waves and are
90° out of phase with each other. These filters are designed with
the assumption that the system clock speed is at or near its
maximum speed (300 MHz). If the system clock speed is much
less than 300 MHz, for example 200 MHz, it is possible, or
inevitable, that unwanted DAC products other than the
fundamental signal will be passed by the low-pass filters.
If an AD9852 evaluation board is used, any reference to the Q
signal should be interpreted to mean the control DAC.
Observing the Filtered IOUT1 and the Filtered IOUT1
The filtered I DAC outputs can be observed at J6 (the true signal)
and J7 (the complementary signal). Use the following procedure to
route the 120 MHz low-pass filters in the true and complementary
output paths of the I DAC to remove images, aliased harmonics,
and other spurious signals above approximately 120 MHz:
1.
Install shorting jumpers at W7 and W10.
2.
Install a shorting jumper at W16.
3.
Install a shorting jumper on Pin 2 and Pin 3 (top two pins)
of the 3-pin W1 header.
4.
Install a shorting jumper on Pin 2 and Pin 3 (top two pins)
of the 3-pin W4 header.
5.
Install a shorting jumper on Pin 2 and Pin 3 (bottom two pins)
of the 3-pin W2 and W8 headers.
The resulting signals appear as nearly pure sine waves and are
180° out of phase with each other. If the system clock speed is
much less than 300 MHz, for example 200 MHz, it is possible,
or inevitable, that unwanted DAC products other than the
fundamental signal will be passed by the low-pass filters.
Connecting the High Speed Comparator
To connect the high speed comparator to the DAC output
signals use either the quadrature filtered output configuration
(AD9854 only) or the complementary filtered output configuration
(both AD9854 and AD9852). Follow Step 1 through Step 4 of
IOUT2 section or the Observing the Filtered IOUT1 and the
Filtered IOUT1 section. Then install a shorting jumper on Pin 1
and Pin 2 (the top two pins) of the 3-pin W2 and W8 headers.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9854ASTZ | IC DDS QUADRATURE CMOS 80-LQFP |
| AD9858BSVZ | IC DDS DAC 10BIT 1GSPS 100-TQFP |
| AD9859YSVZ-REEL7 | IC DDS DAC 10BIT 400MSPS 48TQFP |
| AD9880KSTZ-100 | IC INTERFACE/HDMI 100MHZ 100LQFP |
| AD9882KSTZ-140 | IC INTERFACE/DVI 100MHZ 100LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9852ASVZ | 制造商:Analog Devices 功能描述:IC DDS 300MHz TQFP-80 制造商:Analog Devices 功能描述:IC, DDS, 300MHz, TQFP-80 |
| AD9852ASVZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS |
| AD9852BSVZ | 制造商:Analog Devices 功能描述: |
| AD9853 | 制造商:AD 制造商全称:Analog Devices 功能描述:Programmable Digital OPSK/16-QAM Modulator |
| AD9853-45PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Programmable Digital OPSK/16-QAM Modulator |
发布紧急采购，3分钟左右您将得到回复。