参数资料
| 型号： | AD9852ASVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/52页 |
| 文件大小： | 0K |
| 描述： | IC DDS SYNTHESIZER CMOS 80-TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 12 b |
| 主 fclk： | 300MHz |
| 调节字宽（位）： | 48 b |
| 电源电压： | 3.14 V ~ 3.47 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-TQFP 裸露焊盘 |
| 供应商设备封装： | 80-TQFP-EP（12x12） |
| 包装： | 托盘 |
| 配用： | AD9852/PCBZ-ND - BOARD EVAL FOR AD9852 |
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AD9852
Rev. E | Page 30 of 52
PLL Filter
The PLL FILTER pin (Pin 61) provides the connection for the
external zero-compensation network of the PLL loop filter. The
zero-compensation network consists of a 1.3 kΩ resistor in
series with a 0.01 μF capacitor. The other side of the network
should be connected as close as possible to Pin 60 (AVDD). For
optimum phase noise performance, the clock multiplier can be
bypassed by setting the bypass PLL bit in Control Register
Address 1E hex.
Differential REFCLK Enable
A high level on the DIFF CLK ENABLE pin enables the differential
clock inputs, REFCLK (Pin 69) and REFCLK (Pin 68). The min-
imum differential signal amplitude required is 400 mV p-p at
the REFCLK input pins. The center point or common-mode
range of the differential signal can range from 1.6 V to 1.9 V.
When Pin 64 (DIFF CLK ENABLE) is tied low, REFCLK (Pin 69)
is the only active clock input. This is referred to as single-ended
mode. In this mode, Pin 68 (REFCLK) should be tied low or high.
HIGH SPEED COMPARATOR
The comparator is optimized for high speed and has a toggle
rate greater than 300 MHz, low jitter, sensitive input, and built-
in hysteresis. It also has an output level of 1 V p-p minimum into
50 Ω or CMOS logic levels into high impedance loads. The com-
parator can be powered down separately to conserve power. This
comparator is used in clock-generator applications to square up
the filtered sine wave generated by the DDS.
POWER-DOWN
The programming registers allow several individual stages to be
powered down to reduce power consumption while maintaining
the functionality of the desired stages. These stages are identified in
the Register Layout table (Table 9) in the Address 1D hex section.
Power-down is achieved by setting the specified bits to logic high.
A logic low indicates that the stages are powered up.
Furthermore, and perhaps most importantly, the inverse sinc
filters and the digital multiplier stages can be bypassed to achieve
significant power reduction by programming the control regis-
ters in Address 20 hex. Again, logic high causes the stage to be
bypassed. Of particular importance is the inverse sinc filter
because this stage consumes a significant amount of power.
A full power-down occurs when all four PD bits in Control
Register 1D hex are set to logic high. This reduces power
consumption to approximately 10 mW (3 mA).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9852ASVZ | 制造商:Analog Devices 功能描述:IC DDS 300MHz TQFP-80 制造商:Analog Devices 功能描述:IC, DDS, 300MHz, TQFP-80 |
| AD9852ASVZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS |
| AD9852BSVZ | 制造商:Analog Devices 功能描述: |
| AD9853 | 制造商:AD 制造商全称:Analog Devices 功能描述:Programmable Digital OPSK/16-QAM Modulator |
| AD9853-45PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Programmable Digital OPSK/16-QAM Modulator |
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