参数资料
| 型号： | AD9974BBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/52页 |
| 文件大小： | 0K |
| 描述： | IC CCDSP DUAL 14BIT 100-CSPBGA |
| 标准包装： | 1 |
| 类型： | CCD 信号处理器，14 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 55mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LFBGA，CSPBGA |
| 供应商设备封装： | 100-CSBGA（9x9） |
| 包装： | 标准包装 |
| 其它名称： | AD9974BBCZRLDKR |
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AD9974
Rev. A | Page 19 of 52
Table 11. CLPOB and PBLK Pattern Registers
Parameter
Length (Bits)
Range
Description
CLPOB0_TOG1
13
0 to 8191 pixel location
First CLPOB0 toggle position within the line for each V-sequence.
CLPOB0_TOG2
13
0 to 8191 pixel location
Second CLPOB0 toggle position within the line for each V-sequence.
CLPOB1_TOG1
13
0 to 8191 pixel location
First CLPOB1 toggle position within the line for each V-sequence.
CLPOB1_TOG2
13
0 to 8191 pixel location
Second CLPOB1 toggle position within the line for each V-sequence.
CLPOB_POL
9
High/low
Starting polarity of CLPOB for each V-sequence [8:0] (in field registers).
CLPOB_PAT
9
0 to 9 settings
CLPOB pattern selection for each V-sequence [8:0] (in field registers).
CLPOBMASKSTART
13
0 to 8191 pixel location
CLPOB mask start position: three values available (in field registers).
CLPOBMASKEND
13
0 to 8191 pixel location
CLPOB mask end position: three values available (in field registers).
PBLK0_TOG1
13
0 to 8191 pixel location
First PBLK0 toggle position within the line for each V-sequence.
PBLK0_TOG2
13
0 to 8191 pixel location
Second PBLK0 toggle position within the line for each V-sequence.
PBLK1_TOG1
13
0 to 8191 pixel location
First PBLK1 toggle position within the line for each V-sequence.
PBLK1_TOG2
13
0 to 8191 pixel location
Second toggle position within the line for each V-sequence.
PBLK_POL
9
High/low
Starting polarity of PBLK for each V-sequence [8:0] (in field registers).
PBLK_PAT
9
0 to 9 settings
PBLK pattern selection for each V-sequence [8:0] (in field registers).
PBLKMASKSTART
13
0 to 8191 pixel location
PBLK mask start position: three values available (in field registers).
PBLKMASKEND
13
0 to 8191 pixel location
PBLK mask end position: three values available (in field registers).
HD
HBLK
BASIC HBLK PULSE IS GENERATED USING HBLKTOGE1 AND HBLKTOGE2 REGISTERS (HBLKALT = 0).
BLANK
HBLKTOGE1
HBLKTOGE2
05
95
5-
0
25
Figure 25. Typical Horizontal Blanking Pulse Placement (HBLKMODE = 0)
HD
HBLK
H1/H3
H2/H4
THE POLARITY OF H1/H3 DURING BLANKING IS PROGRAMMABLE
(H2/H4 POLARITY IS SEPARATELY PROGRAMMABLE)
05
95
5-
02
6
Figure 26. HBLK Masking Control
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