参数资料
| 型号： | AD9974BBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/52页 |
| 文件大小： | 0K |
| 描述： | IC CCDSP DUAL 14BIT 100-CSPBGA |
| 标准包装： | 1 |
| 类型： | CCD 信号处理器，14 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 55mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LFBGA，CSPBGA |
| 供应商设备封装： | 100-CSBGA（9x9） |
| 包装： | 标准包装 |
| 其它名称： | AD9974BBCZRLDKR |
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AD9974
Rev. A | Page 35 of 52
NOTES
1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE.
2. INTERNAL H-COUNTER IS ALWAYS RESET 11.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE.
3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 12 OR 13 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHPLOC = 0 IS SHOWN IN THE ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 12 CLI RISING EDGES AFTER HD FALLING EDGE.
5. HD FALLING EDGE SHOULD OCCUR COINCIDENT WITH VD FALLING EDGE (WITHIN SAME CLI CYCLE) OR AFTER VD FALLING EDGE. HD FALLING
EDGE SHOULD NOT OCCUR WITHIN 1 AND 5 CLI CYCLES IMMEDIATELY BEFORE VD FALLING EDGE.
VD
HD
CLI
3ns MIN
tCLIDLY
11.5 CYCLES
XXX XXXX XXX XXXX 0
1 2
tVDHD
H-COUNTER
RESET
SHD
INTERNAL
HD
INTERNAL
H-COUNTER
(PIXEL COUNTER)
3ns MIN
05
95
5-
04
9
Figure 49. Horizontal Counter Pipeline Delay
VD
HD
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 12 PIXELS OF PIXEL 0 LOCATION.
H-COUNTER
(PIXEL COUNTER)
H-COUNTER
RESET
X
N– 11 N– 10 N –9 N–8 N– 7 N–6 N– 5 N– 4 N– 3 N– 2 N –1
0
1
2
N
0
5955-
050
Figure 50. No-Toggle Positions
Additional Restrictions
If possible, perform all start-up serial writes with VD and
HD disabled. This prevents unknown behavior caused by
partial updating of registers before all information is loaded.
When operating, note the following restrictions:
The HD falling edge should be located in the same CLI
clock cycle as the VD falling edge or later than the VD
falling edge. The HD falling edge should not be located
within 1 cycle prior to the VD falling edge.
The internal horizontal counter is reset 12 CLI cycles after the
falling edge of HD. See Figure 49 for details on how the internal
counter is reset.
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