参数资料
| 型号： | AD9974BBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/52页 |
| 文件大小： | 0K |
| 描述： | IC CCDSP DUAL 14BIT 100-CSPBGA |
| 标准包装： | 1 |
| 类型： | CCD 信号处理器，14 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 55mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LFBGA，CSPBGA |
| 供应商设备封装： | 100-CSBGA（9x9） |
| 包装： | 标准包装 |
| 其它名称： | AD9974BBCZRLDKR |
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AD9974
Rev. A | Page 20 of 52
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 25 is similar
to CLPOB and PBLK; however, there is no start polarity control.
Only the toggle positions designate the start and the stop positions
of the blanking period. Additionally, as shown in Figure 26, there
is a polarity control, HBLKMASK, for H1/H3 and H2/H4 that
designates the polarity of the horizontal clock signals during the
blanking period. Setting HBLKMASK_H1 low sets H1 = H3 =
low and HBLKMASK_H2 high sets H2 = H4 = high during the
blanking. As with the CLPOB and PBLK signals, HBLK registers
are available in each H-pattern group, allowing unique blanking
signals to be used with different vertical timing sequences.
The AD9974 supports three modes of HBLK operation. HBLK
Mode 0 supports basic operation and provides some support for
special HBLK patterns. HBLK Mode 1 supports pixel mixing
HBLK operation. HBLK Mode 2 supports advanced HBLK opera-
tion. The following sections describe each mode. Register
parameters are detailed in Table 12.
HBLK Mode 0 Operation
There are six toggle positions available for HBLK. Normally,
only two of the toggle positions are used to generate the standard
HBLK interval. However, the additional toggle positions can be
used to generate special HBLK patterns, as shown in Figure 27.
The pattern in this example uses all six toggle positions to generate
two extra groups of pulses during the HBLK interval. By changing
the toggle positions, different patterns are created.
Separate toggle positions are available for even and odd lines.
If alternation is not needed, load the same values into the registers
for even (HBLKTOGE) and odd (HBLKTOGO) lines.
HBLK
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS (HBLKALT = 0).
H1/H3
H2/H4
HBLKTOGE1
HBLKTOGE2
HBLKTOGE3
HBLKTOGE4
HBLKTOGE5
HBLKTOGE6
0
595
5-
0
27
Figure 27. Generating Special HBLK Patterns
Table 12. HBLK Pattern Registers
Register
Length (Bits)
Range
Description
HBLK_MODE
2
0 to 2 HBLK modes
Enables different HBLK toggle position operations.
0 = normal mode. Six toggle positions available for even and odd lines.
If even/odd alternation is not needed, set toggles for even/odd the same.
1 = pixel mixing mode. In addition to six toggle positions, the HBLKSTART,
HBLKEND, HBLKLEN, and HBLKREP registers can be used to generate HBLK
patterns. If even/odd alternation is not needed, set toggles for even/odd
the same.
2 = advanced HBLK mode. Divides HBLK interval into six different repeat
areas. Uses HBLKSTARTA/B/C and RA*H*REPA/B/C registers.
3 = test mode only. Do not access.
HBLKSTART
13
0 to 8191 pixel location
Start location for HBLK in HBLK Mode 1 and HBLK Mode 2.
HBLKEND
13
0 to 8191 pixel location
End location for HBLK in HBLK Mode 1 and HBLK Mode 2.
HBLKLEN
13
0 to 8191 pixels
HBLK length in HBLK Mode 1 and HBLK Mode 2.
HBLKREP
13
0 to 8191 repetitions
Number of HBLK repetitions in HBLK Mode 1 and HBLK Mode 2.
HBLKMASK_H1
1
High/low
Masking polarity for H1 and H3 during HBLK.
HBLKMASK_H2
1
High/low
Masking polarity for H2 and H4 during HBLK.
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相关代理商/技术参数 |
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| AD9975 | 制造商:AD 制造商全称:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABST | 制造商:AD 制造商全称:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABSTEB | 制造商:AD 制造商全称:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABSTRL | 制造商:AD 制造商全称:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975BST | 制造商:Analog Devices 功能描述:Mixed Signal Front End 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT ANALOG FRONT END WITH HALF DUPLEX - Tape and Reel |
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