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| 型号： | ADAU1445YSVZ-3A-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 55/92页 |
| 文件大小： | 0K |
| 描述： | IC SIGMADSP 175MHZ 100TQFP |
| 标准包装： | 1,000 |
| 系列： | SigmaDSP® |
| 类型： | 音频处理器 |
| 应用： | 车载音频 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 带卷 (TR) |
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ADAU1445/ADAU1446
Rev. A | Page 59 of 92
Numeric Formats
DSP systems commonly use a standard numeric format.
Fractional number systems are specified by an A.B format,
where A is the number of bits to the left of the decimal point
and B is the number of bits to the right of the decimal point.
The ADAU1445/ADAU1446 use the same numeric format for
both the parameter and data values. The format is as shown in
the Numerical Format: 5.23 section.
Numerical Format: 5.23
Linear range: –16.0 to (+16.0 1 LSB)
Examples:
1000 0000 0000 0000 0000 0000 0000 = 16.0
1110 0000 0000 0000 0000 0000 0000 = 4.0
1111 1000 0000 0000 0000 0000 0000 = 1.0
1111 1110 0000 0000 0000 0000 0000 = 0.25
1111 1111 0011 0011 0011 0011 0011 = 0.1
1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0.0)
0000 0000 0000 0000 0000 0000 0000 = 0.0
0000 0000 1100 1100 1100 1100 1101 = 0.1
0000 0010 0000 0000 0000 0000 0000 = 0.25
0000 1000 0000 0000 0000 0000 0000 = 1.0
0010 0000 0000 0000 0000 0000 0000 = 4.0
0111 1111 1111 1111 1111 1111 1111 = (16.0 – 1 LSB).
The serial port accepts up to 24 bits of input and is sign-
extended to the full 28 bits of the DSP core. This allows internal
gains of up to 24 dB without encountering internal clipping.
A digital clipper circuit is used within the DSP core before
outputting to the serial port outputs, ASRCs, and S/PDIF
transmitter (see Figure 52). This clips the top four bits of the
signal to produce a 24-bit output with a range of 1.0 (minus
1 LSB) to –1.0. Figure 52 shows the maximum signal levels at
each point in the data flow in both binary and decibel levels.
4-BIT SIGN EXTENSION
SDATA_INx
1.23
(0dB)
1.23
(0dB)
1.23
(0dB)
5.23
(24dB)
5.23
(24dB)
SERIAL
PORT
SIGNAL
PROCESSING
(5.23 FORMAT)
DIGITAL
CLIPPER
0769
6-
053
Figure 52. Numeric Precision and Clipping Structure (TBD)
Programming
On power-up, the ADAU1445/ADAU1446 have no default
program loaded. There are 3584 instruction cycles per audio
sample, resulting in an internal clock rate of 172.032 MHz when
fS,NORMAL is 48 kHz. The DSP runs in a stream-oriented manner,
meaning that all 3584 instructions are executed each sample
period. The ADAU1445/ADAU1446 can also be set up to accept
dual- or quad-speed inputs by reducing the number of
instructions per sample. These modes can be set in the core
control register.
The ADAU1445/ADAU1446 can be programmed easily using
SigmaStudio, an entirely graphical tool provided by Analog
Devices. No knowledge of writing line-level DSP code is required,
and the large library of predesigned algorithms should drastically
reduce development time. More information on SigmaStudio
can be found at the Analog Devices website.
Program Counter
The execution of instructions in the core is governed by a
program counter, which sequentially steps through the
addresses of the program RAM. The program counter starts
every time a new audio frame is clocked into the core.
SigmaStudio inserts a jump-to-start command at the end of
every program. The program counter increments sequentially
until reaching this command, and then jumps to the program
start address (Program RAM Address 0x2010) and waits for the
next audio frame to clock into the core.
Branching and Looping
Some cells in SigmaStudio can optionally modify the program
counter to implement simple branching and looping structures.
However, care must be taken that the program counter returns
to its starting address before a new frame is clocked. If the new
frame starts before the counter has returned to start, the audio
output is corrupted, and a reset is necessary.
The software compiler in SigmaStudio calculates the maximum
possible program cycles for a given project and generates an
error when a user exceeds the allowable limit.
DSP CORE MODES AND SETTINGS
Core Run Register (Address 0xE228)
Table 39. Descriptions of Register 0xE228
Bit Position
Description
Default
[15:1]
Reserved
[0]
Core run bit
0
This single-bit register initiates the run signal to start the core.
This should be the very last register that is set when the system
is initialized.
If the core is halted (that is, if Bit 0 of Register 0xE228 is set to
0) during operation, the serial outputs slew to 0. This ensures
that no dc level is left on the serial outputs and helps prevent
speaker damage in the system. It also allows the system to mute
and unmute all audio channels while minimizing pops and
clicks on the outputs.
The core run bit can be used to implement a system mute
functionality, as opposed to muting all of the individual
channels in software.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADAU1446EBZ | 制造商:Analog Devices 功能描述:SIGMADSP? DIGITAL AUDIO PROCESSOR WITH FLEXIBLE AUDIO - Bulk |
| ADAU1446YSTZ-3A | 功能描述:IC SIGMADSP 175MHZ 100LQFP RoHS:是 类别:集成电路 (IC) >> 线性 - 音频处理 系列:SigmaDSP® 其它有关文件:STA321 View All Specifications 标准包装:1 系列:Sound Terminal™ 类型:音频处理器 应用:数字音频 安装类型:表面贴装 封装/外壳:64-LQFP 裸露焊盘 供应商设备封装:64-LQFP EP（10x10） 包装:Digi-Reel® 其它名称:497-11050-6 |
| ADAU1446YSTZ-3A-RL | 功能描述:IC SIGMADSP 175MHZ 100LQFP RoHS:是 类别:集成电路 (IC) >> 线性 - 音频处理 系列:SigmaDSP® 其它有关文件:STA321 View All Specifications 标准包装:1 系列:Sound Terminal™ 类型:音频处理器 应用:数字音频 安装类型:表面贴装 封装/外壳:64-LQFP 裸露焊盘 供应商设备封装:64-LQFP EP（10x10） 包装:Digi-Reel® 其它名称:497-11050-6 |
| ADAU1450WBCPZ | 功能描述:IC AUDIO PROCESSOR 72LFCSP 制造商:analog devices inc. 系列:SigmaDSP? 包装:托盘 零件状态:有效 类型:Sigma 接口:I2C，SPI 时钟速率:147.456MHz 非易失性存储器:- 片载 RAM:64KB 电压 - I/O:3.3V 电压 - 内核:1.20V 工作温度:-40°C ~ 105°C（TA） 安装类型:表面贴装 封装/外壳:72-VFQFN 裸露焊盘，CSP 供应商器件封装:72-LFCSP-VQ（10x10） 标准包装:1 |
| ADAU1450WBCPZ-RL | 功能描述:IC AUDIO PROCESSOR 72LFCSP 制造商:analog devices inc. 系列:SigmaDSP? 包装:剪切带（CT） 零件状态:在售 类型:Sigma 接口:I2C，SPI 时钟速率:147.456MHz 非易失性存储器:- 片载 RAM:64KB 电压 - I/O:3.30V 电压 - 内核:1.20V 工作温度:-40°C ~ 105°C（TA） 安装类型:表面贴装 封装/外壳:72-VFQFN 裸露焊盘，CSP 供应商器件封装:72-LFCSP-VQ（10x10） 标准包装:1 |
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