参数资料
| 型号： | ADE7116ASTZF8 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 142/152页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 64-LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 160 |
| 输入阻抗： | 770 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2V |
| 电压 - 低输入/输出： | 0.8V |
| 电流 - 电源： | 4mA |
| 电源电压： | 2.4 V ~ 3.7 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
I/O PORTS
PARALLEL I/O
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 use three input/output ports to exchange data with
external devices. In addition to performing general-purpose
I/O, some are capable of driving an LCD or performing alternate
functions for the peripherals available on-chip. In general, when
a peripheral is enabled, the pins associated with it cannot be
used as a general-purpose I/O. The I/O port can be configured
through the SFRs listed in Table 155.
Weak Internal Pull-Ups Enabled
A pin with weak internal pull-up enabled is used as an input by
writing a 1 to the pin. The pin is pulled high by the internal pull-
ups, and the pin is read using the circuitry shown in Figure 116.
If the pin is driven low externally, it sources current because of
the internal pull-ups.
A pin with internal pull-up enabled is used as an output by
writing a 1 or a 0 to the pin to control the level of the output. If
a 0 is written to the pin, it drives a logic low output voltage
Table 155. I/O Port SFRs
SFR Address Bit Addressable
Description
(V OL ) and is capable of sinking 1.6 mA.
Open Drain (Weak Internal Pull-Ups Disabled)
P0
P1
P2
EPCFG
0x80
0x90
0xA0
0x9F
Yes
Yes
Yes
No
Port 0 register.
Port 1 register.
Port 2 register.
Extended port
When the weak internal pull-up on a pin is disabled, the pin
becomes open drain. Use this open-drain pin as a high impedance
input by writing a 1 to the pin. The pin is read using the circuitry
shown in Figure 116. The open-drain option is preferable for
configuration.
inputs because it draws less current than the internal pull-ups
PINMAP0
PINMAP1
PINMAP2
0xB2
0xB3
0xB4
No
No
No
Port 0 weak
pull-up enable.
Port 1 weak
pull-up enable.
Port 2 weak
that were enabled.
38 kHz Modulation
Every ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provides a 38 kHz modulation signal. The 38 kHz
pull-up enable.
The three bidirectional I/O ports have internal pull-ups that can
be enabled or disabled individually for each pin. The internal
pull-ups are enabled by default. Disabling an internal pull-up
causes a pin to become open drain. Weak internal pull-ups are
configured through the PINMAPx SFRs.
Figure 116 shows a typical bit latch and I/O buffer for an I/O
pin. The bit latch (one bit in the SFR of each port) is represented
as a Type D flip-flop, which clocks in a value from the internal
bus in response to a write-to-latch signal from the CPU. The
Q output of the flip-flop is placed on the internal bus in response
to a read latch signal from the CPU. The level of the port pin
itself is placed on the internal bus in response to a read pin
signal from the CPU. Some instructions that read a port activate
the read latch signal, and others activate the read pin signal. See
the Read-Modify-Write Instructions section for details.
DV DD
modulation is accomplished by internally XOR’ing the level
written to the I/O pin with a 38 kHz square wave. Then, when
a 0 is written to the I/O pin, it is modulated as shown in
Figure 117.
LEVEL WRITTEN
TO MOD38
38kHz MODULATION
SIGNAL
OUTPUT AT
MOD38 PIN
Figure 117. 38 kHz Modulation
Uses for this 38 kHz modulation include IR modulation of
a UART transmit signal or a low power signal to drive an
LED. The modulation can be enabled or disabled with the
MOD38EN bit (Bit 4) in the CFG SFR (Address 0xAF). The
38 kHz modulation is available on eight pins, selected by the
MOD38[7:0] bits in the extended port configuration SFR
(EPCFG, Address 0x9F).
READ
LATCH
ALTERNATE
OUTPUT
FUNCTION
INTERNAL
PULL-UP
CLOSED: PINMAPx.x = 0
OPEN: PINMAPx.x = 1
INTERNAL
BUS
D
Q
Px.x
PIN
WRITE
TO LATCH
READ
PIN
CL Q
LATCH
ALTERNATE
INPUT
FUNCTION
Figure 116. Port 0 Bit Latch and I/O Buffer
Rev. B | Page 142 of 1 5 2
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