参数资料
| 型号： | ADE7116ASTZF8 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 93/152页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 64-LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 160 |
| 输入阻抗： | 770 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2V |
| 电压 - 低输入/输出： | 0.8V |
| 电流 - 电源： | 4mA |
| 电源电压： | 2.4 V ~ 3.7 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
INTERRUPT SYSTEM
PSM
The unique power management architecture of the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 includes
an operating mode (PSM2) where the 8052 MCU core is shut
down. Events can be configured to wake the 8052 MCU core
from the PSM2 operating mode. A distinction is drawn here
between events that can trigger the wake-up of the 8052 MCU
core and events that can trigger an interrupt when the MCU
core is active. Events that can wake the core are referred to as
wake-up events, whereas events that can interrupt the program
flow when the MCU is active are called interrupts. See the 3.3 V
Peripherals and Wake-Up Events section to learn more about
events that can wake the 8052 core from PSM2 mode.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provide 12 interrupt sources with three priority levels.
The power management interrupt is at the highest priority level.
The other two priority levels are configurable through the
interrupt priority SFR (IP, Address 0xB8) and the interrupt
enable and Priority 2 SFR (IEIP2, Address 0xA9).
STANDARD 8052 INTERRUPT ARCHITECTURE
A Priority 1 interrupt can interrupt the service routine of a
Priority 0 interrupt, and if two interrupts of different priorities
occur at the same time, the Priority 1 interrupt is serviced first.
An interrupt cannot be interrupted by another interrupt of the
same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed. See the
Interrupt Priority section.
INTERRUPT ARCHITECTURE
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 possess advanced power supply management
features. To ensure a fast response to time-critical power supply
issues, such as a loss of line power, the power supply manage-
ment interrupt should be able to interrupt any interrupt service
routine. To enable the user to have full use of the standard 8052
interrupt priority levels, an additional priority level is added for the
power supply management (PSM) interrupt. The PSM interrupt
is the only interrupt at this highest interrupt priority level.
HIGH
PRIORITY 1
The standard 8052 interrupt architecture includes two tiers of
interrupts, where some interrupts are assigned a high priority
LOW
PRIORITY 0
and others are assigned a low priority.
Figure 88. Interrupt Architecture
HIGH
PRIORITY 1
See the Power Supply Management (PSM) Interrupt section for
PRIORITY 0
LOW
Figure 87. Standard 8052 Interrupt Priority Levels
more information on the PSM interrupt.
INTERRUPT REGISTERS
The control and configuration of the interrupt system are carried
out through four interrupt-related SFRs, discussed in this section.
Table 77. Interrupt SFRs
SFR
IE
IP
IEIP2
WDCON
Address
0xA8
0xB8
0xA9
0xC0
Default
0x00
0x00
0xA0
0x10
Bit Addressable
Yes
Yes
No
Yes
Description
Interrupt enable (see Table 78).
Interrupt priority (see Table 79).
Interrupt enable and Priority 2 (see Table 80).
Watchdog timer (see Table 85 and the Writing to the Watchdog Timer SFR (WDCON,
Address 0xC0) section).
Table 78. Interrupt Enable SFR (IE, Address 0xA8)
Bit
7
6
5
4
3
2
1
0
Bit Address
0xAF
0xAE
0xAD
0xAC
0xAB
0xAA
0xA9
0xA8
Mnemonic
EA
ETEMP 1
ET2
ES
ET1
EX1
ET0
EX0
Description
Enables all interrupt sources. Set by the user. Cleared by the user to disable all interrupt sources.
Enables the temperature ADC interrupt. Set by the user.
Enables the Timer 2 interrupt. Set by the user.
Enables the UART serial port interrupt. Set by the user.
Enables the Timer 1 interrupt. Set by the user.
Enables External Interrupt 1 (INT1). Set by the user.
Enables the Timer 0 interrupt. Set by the user.
Enables External Interrupt 0 (INT0). Set by the user.
1
This feature is not available in the ADE7116.
Rev. B | Page 93 of 152
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| ADE7116ASTZF8-RL | 功能描述:IC ENERGY METER 64-LQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
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