参数资料
| 型号： | ADE7116ASTZF8 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/152页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 64-LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 160 |
| 输入阻抗： | 770 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2V |
| 电压 - 低输入/输出： | 0.8V |
| 电流 - 电源： | 4mA |
| 电源电压： | 2.4 V ~ 3.7 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Pin No.
18
19
20 to 35
36
37
38
39
40
41
42
43
44
45
46
47
48
49, 50
51
52, 53
54
55
56
57
58
Mnemonic
LCDVA
LCDVP1
FP15 to FP0
P1.1/TxD
P1.0/RxD
P0.7/SS/T1
P0.6/SCLK/T0
P0.5/MISO
P0.4/MOSI/SDATA
P0.3/CF2
P0.2/CF1/RTCCAL
SDEN/P2.3
BCTRL/INT1/P0.0
XTAL2
XTAL1
INT0
V P , V N
EA
I PA , I N
AGND
I PB
RESET
REF IN/OUT
V BAT
Description
In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or
an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an
analog input. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this
pin is an analog input, a resistor should be connected between this pin and LCDVP1 to generate an inter-
mediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this
pin and LCDVB to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVA and LCDVB are
internally connected (see the LCD Driver section).
In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or
an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an
analog input. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and
LCDVP2. When this pin is an analog input, a resistor should be connected between this pin and LCDVA to
generate an intermediate voltage for the LCD driver. Another resistor must be connected between LCDVP1
and DGND to generate another intermediate voltage (see the LCD Driver section).
LCD Segment Output 0 to LCD Segment Output 15.
General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).
General-Purpose Digital I/O Port 1.0/Receiver Data Input (Asynchronous).
General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input.
General-Purpose Digital I/O Port 0.6/Clock Output for I 2 C or SPI Port/Timer 0 Input.
General-Purpose Digital I/O Port 0.5/Data Input for SPI Port.
General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I 2 C-Compatible Data Line.
General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, I rms , or apparent power information.
General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic
Output. The CF1 logic output gives instantaneous active, reactive, I rms , or apparent power information. The
RTCCAL logic output gives access to the calibrated RTC output.
Serial Download Mode Enable/General-Purpose Digital I/O Port 2.3. This pin is used to enable serial
download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily
becomes an input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin
momentarily goes high and then user code is executed. If the pin is pulled down on reset, the embedded
serial download/debug kernel executes, and this pin remains low during the internal program execution.
After reset, this pin can be used as a digital output port pin (P2.3).
Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic
input connects V DD or V BAT to V SWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between V DD or V BAT and V SWOUT is selected internally.
A crystal can be connected across this pin and XTAL1 to provide a clock source for the ADE7116/ADE7156/
ADE7166/ADE7169. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or
by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin.
An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected
across XTAL1 and XTAL2 to provide a clock source for the ADE7116/ADE7156/ADE7166/ADE7169. The clock
frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.
External Interrupt Input 0.
Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.
This pin is used as an input for emulation. When held high, this input enables the device to fetch code from
internal program memory locations. The ADE7116/ADE7156/ADE7166/ADE7169 do not support external
code memory. This pin should not be left floating.
Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.
This pin provides the ground reference for the analog circuitry.
Analog Input for Second Current Channel (I PB ). This input is fully differential with a maximum differential
level of ±400 mV, referred to I N for specified operation. This channel also has an internal PGA.
Reset Input, Active Low.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
1.2 V ± 0.1% and a maximum temperature coefficient of 50 ppm/°C. This pin should be decoupled with a 1
μF capacitor in parallel with a ceramic 100 nF capacitor.
Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to V DD when
the battery is selected as the power supply for the ADE7116/ADE7156/ADE7166/ADE7169.
Rev. B | Page 20 of 15 2
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