参数资料
| 型号： | ADE7116ASTZF8 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 98/152页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 64-LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 160 |
| 输入阻抗： | 770 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2V |
| 电压 - 低输入/输出： | 0.8V |
| 电流 - 电源： | 4mA |
| 电源电压： | 2.4 V ~ 3.7 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
WATCHDOG TIMER
The watchdog timer generates a device reset or interrupt within
a reasonable amount of time if the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569 enter an erroneous state, possibly
due to a programming error or electrical noise. The watchdog is
enabled by default with a timeout of two seconds and creates a
system reset if not cleared within two seconds. The watchdog
function can be disabled by clearing the watchdog enable bit
(WDE, Bit 1) in the watchdog timer SFR (WDCON, Address
0xC0).
The watchdog circuit generates a system reset or interrupt
(WDS, Bit 2) if the user program fails to set the WDE bit within
a predetermined amount of time (set by the PRE bits).
The watchdog timer is clocked from the 32.768 kHz external
crystal connected between the XTAL1 and XTAL2 pins.
Table 85. Watchdog Timer SFR (WDCON, Address 0xC0)
The WDCON SFR can be written to by user software only if the
double write sequence described in Table 85 is initiated on
every write access to the WDCON SFR.
To prevent any code from inadvertently disabling the watchdog, a
watchdog protection can be activated. This watchdog protection
locks in the watchdog enable and event settings so they cannot
be changed by user code. The protection is activated by clearing
a watchdog protection bit in the flash memory. The watchdog
protection bit is the most significant bit at Address 0x3FFA of
the flash memory. When this bit is cleared, the WDIR bit (Bit 3) is
forced to 0, and the WDE bit is forced to 1. Note that the
sequence for configuring the flash protection bits must be
followed to modify the watchdog protection bit at Address
0x3FFA (see the Protecting the Flash section).
Bit
[7:4]
Address
0xC7 to
Mnemonic
PRE
Default
7
Description
Watchdog prescaler. In normal mode, the 16-bit watchdog timer is clocked by the input
0xC4
clock (32.768 kHz). The PRE bits set which of the upper bits of the counter are used as the
watchdog output, as follows:
t WATCHDOG = 2 PRE ×
PRE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010 to 1111
2 9
CLKIN
Result (Watchdog Timeout)
15.6 ms
31.2 ms
62.5 ms
125 ms
250 ms
500 ms
1 sec
2 sec
0 sec, automatic reset
0 sec, serial download reset
Not a valid selection
3
0xC3
WDIR
0
Watchdog interrupt response bit. When cleared, the watchdog generates a system reset
when the watchdog timeout period has expired. When set, the watchdog generates an
interrupt when the watchdog timeout period has expired.
2
0xC2
WDS
0
Watchdog status bit. This bit is set to indicate that a watchdog timeout has occurred. It is
cleared by writing a 0 or by an external hardware reset. A watchdog reset does not clear
WDS; therefore, it can be used to distinguish between a watchdog reset and a hardware
reset from the RESET pin.
1
0xC1
WDE
1
Watchdog enable bit. When set, this bit enables the watchdog and clears its counter. The
watchdog counter is subsequently cleared again whenever WDE is set. If the watchdog is
not cleared within its selected timeout period, it generates a system reset or watchdog
interrupt, depending on the WDIR bit.
0
0xC0
WDWR
0
Watchdog write enable bit (see the Writing to the Watchdog Timer SFR (WDCON, Address
0xC0) section).
Rev. B | Page 98 of 152
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