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| 型号： | ADN2818ACPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/40页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-LFCSP |
| 标准包装： | 1,500 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | CML |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.7GHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
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Data Sheet
ADN2817/ADN2818
Rev. E | Page 25 of 40
Voltage Output Mode of Operation
A second mode of operation is the voltage output mode. This
mode is to give easy access to a coarse estimate of the BER. The
functionality is similar to that already described in the Brief
Overview of Modes of Operation section except that the
measurement is performed autonomously by the ADN2817,
and the result is output as a voltage on a pin from which the
actual BER can be inferred. Because this mode does not perform
scanning of the eye to separate out deterministic jitter from
random jitter effects, this method is less accurate under normal
applied jitter conditions.
The user merely has to bring the BERMODE pin low and read
the voltage on the VBER pin (see Figure 32). Alternatively, a
6-bit value can be read over the I2C.
LOG (BER)
VB
ER
PI
N
VO
L
T
A
G
E
R
EL
A
T
IVE
T
O
VEE
(V)
0.9
0.7
0.5
0.3
0.1
VBER VOLTAGE IS
GUARANTEED TO
SATURATE FOR
INPUT BERs
GREATER THAN 0.001
VBER VOLTAGE IS
GUARANTEED TO
SATURATE FOR
INPUT BERs LESS
THAN 0.000000001
0.001
0.00001
0.0000001
0.000000001
06001-
024
Figure 32. VBER vs. Bit Error Rate
SQUELCH MODE
Two squelch modes are available with the ADN2817/ADN2818:
squelch DATAOUT and CLKOUT mode, and squelch DATAOUT
or CLKOUT mode.
Squelch DATAOUT and CLKOUT mode is selected when
CTRLC[1] = 0 (default mode). In this mode, when the squelch
input, Pin 27, is driven to a TTL high state, both the clock and
data outputs are set to the zero state to suppress downstream
processing. If the squelch function is not required, Pin 27 should be
tied to VEE.
Squelch DATAOUT or CLKOUT mode is selected when
CTRLC[1] is 1. In this mode, when the squelch input is driven
to a high state, the DATAOUT pins are squelched. When the
squelch input is driven to a low state, the CLKOUT pins are
squelched. This is especially useful in repeater applications,
where the recovered clock may not be needed.
I2C INTERFACE
The ADN2817/ADN2818 support a 2-wire, I2C-compatible
serial bus driving multiple peripherals. Two inputs, serial data
(SDA) and serial clock (SCK), carry information between any
devices connected to the bus. Each slave device is recognized by
a unique address. The ADN2817/ADN2818 have two possible
7-bit slave addresses for both read and write operations. The
MSB of the 7-bit slave address is factory programmed to 1. Bit 5
of the slave address is set by Pin 19, SADDR5. Slave Address
Bits[4:0] are defaulted to all 0s. The slave address consists of the
7 MSBs of an 8-bit word. The LSB of the word either sets a read
or write operation (see Figure 18). Logic 1 corresponds to a read
operation and Logic 0 corresponds to a write operation.
To control the device on the bus, the following protocol must be
used. First, the master initiates a data transfer by establishing a
start condition, defined by a high-to-low transition on SDA
while SCK remains high. This indicates that an address/data
stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address and the R/W bit).
The bits are transferred from MSB to LSB. The peripheral that
recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDA and SCK lines waiting for
the start condition and correct transmitted address. The R/W
bit determines the direction of the data. Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.
The ADN2817/ADN2818 act as standard slave devices on the
bus. The data on the SDA pin is eight bits long, supporting the
7-bit addresses plus the R/W bit. The ADN2817/ADN2818 have
eight subaddresses to enable the user-accessible internal registers
byte as the device address and the second byte as the starting
subaddress. Auto-increment mode is supported, allowing data
to be read from, or written to, the starting subaddress and each
subsequent address without manually addressing the subsequent
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all registers.
Stop and start conditions can be detected at any stage of the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCK high period, the
user should issue one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADN2817/ADN2818
do not issue an acknowledge and return to the idle condition.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADN2819 | 制造商:AD 制造商全称:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819ACP-CML | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP Tray 制造商:Rochester Electronics LLC 功能描述:MULTI-RATE 2.7GBPS CDR/ PA LOW POWER I.C - Bulk |
| ADN2819ACP-CML-RL | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R |
| ADN2819ACPZ-CML | 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ADN2819ACPZ-CML1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
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