参数资料
型号: ADN2818ACPZ-RL7
厂商: Analog Devices Inc
文件页数: 3/40页
文件大小: 0K
描述: IC CLOCK/DATA RECOVERY 32-LFCSP
标准包装: 1,500
类型: 时钟和数据恢复(CDR),多路复用器
PLL:
主要目的: SONET/SDH
输入: CML
输出: CML
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 是/是
频率 - 最大: 2.7GHz
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘,CSP
供应商设备封装: 32-LFCSP-VQ(5x5)
包装: 带卷 (TR)
Data Sheet
ADN2817/ADN2818
Rev. E | Page 11 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VB
ER
V
CC
VEE
DAT
AO
UT
P
DAT
AO
UT
N
S
Q
UE
L
CH
CL
KO
UT
P
CL
KO
UT
N
T
HRADJ
RE
F
CL
KP
RE
F
CL
KN
V
CC
VEE
CF
2
CF
1
LOL
BERMODE
VCC
VREF
NIN
PIN
SLICEP
SLICEN
VEE
VCC
VEE
LOS
SDA
SCK
SADDR5
VCC
VEE
06001-
004
NOTES
1. EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE
MUST BE CONNECTED TO VEE.
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
1
12
13
14
15
16
32
31
30
29
28
27
26
25
TOP VIEW
(Not to Scale)
ADN2817/
ADN2818
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
BERMODE
DI
Set this pin to logic low to enable analog voltage output mode for BER monitor.
2
VCC
P
Power for Input Stage, LOS.
3
VREF
AO
Internal VREF Voltage. Decouple to ground with a 0.1 F capacitor.
4
NIN
AI
Differential Data Input. CML.
5
PIN
AI
Differential Data Input. CML.
6
SLICEP
AI
Differential Slice Level Adjust Input.
7
SLICEN
AI
Differential Slice Level Adjust Input.
8
VEE
P
GND for the Limiting Amplifier, LOS.
9
THRADJ
AI
LOS Threshold Setting Resistor.
10
REFCLKP
DI
Differential REFCLK Input. 10 MHz to 200 MHz.
11
REFCLKN
DI
Differential REFCLK Input. 10 MHz to 200 MHz.
12
VCC
P
VCO Power.
13
VEE
P
VCO Ground.
14
CF2
AO
Frequency Loop Capacitor.
15
CF1
AO
Frequency Loop Capacitor.
16
LOL
DO
Loss of Lock Indicator. Active high, LVTTL.
17
VEE
P
FLL Detector Ground.
18
VCC
P
FLL Detector Power.
19
SADDR5
DI
Slave Address Bit 5.
20
SCK
DI
I2C Clock Input.
21
SDA
DI
I2C Data Input.
22
LOS
DO
Loss of Signal Detect Output. Active high, LVTTL.
23
VEE
P
Output Buffer, I2C Ground.
24
VCC
P
Output Buffer, I2C Power.
25
CLKOUTN
DO
Differential Recovered Clock Output. CML.
26
CLKOUTP
DO
Differential Recovered Clock Output. CML.
27
SQUELCH
DI
Disable Clock and Data Outputs. Active high, LVTTL.
28
DATAOUTN
DO
Differential Recovered Data Output. CML.
29
DATAOUTP
DO
Differential Recovered Data Output. CML.
30
VEE
P
Phase Detector, Phase Shifter Ground.
31
VCC
P
Phase Detector, Phase Shifter Power.
32
VBER
AO
This pin represents BER when analog BERMON is enabled with 3 k to VEE.
EP
EPAD
P
Exposed Paddle. The Exposed paddle on the bottom of the package must be connected
to VEE.
1
P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
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