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| 型号： | ADN2818ACPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/40页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-LFCSP |
| 标准包装： | 1,500 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | CML |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.7GHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
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Data Sheet
ADN2817/ADN2818
Rev. E | Page 27 of 40
The user can specify a fixed integer multiple of the reference
clock to lock onto using CTRLA[5:2], where CTRLA should be
set to the data rate/DIV_FREF and DIV_FREF represents the
divided-down reference referred to the 10 MHz to 25 MHz band.
For example, if the reference clock frequency is 38.88 MHz and
the input data rate is 622.08 Mbps, then CTRLA[7:6] is set to 01
to give a divided-down reference clock of 19.44 MHz. CTRLA[5:2]
is set to 0101, that is, 5, because
622.08 Mbps/19.44 MHz = 25
When the CTRLA[7:2] value is correct and CTRLA[0] has been
written to a Logic 1, it is recommended that a 1-to-0 transition
be written to CTRLB[5] to initiate a new frequency acquisition
with respect to the reference clock.
In this mode, if the ADN2817/ADN2818 lose lock for any
reason, they relock onto the reference clock and continue to
output a stable clock.
Though the ADN2817/ADN2818 operate in LTR mode, if
the user ever changes the reference frequency, the fREF range
(CTRLA[7:6]), or the DIV_FREF ratio (CTRLA[5:2]), this must
be followed by writing a 1-to-0 transition into the CTRLB[5] bit
to initiate a new frequency acquisition.
A frequency acquisition can also be initiated in LTR mode by
writing a 0-to-1 transition into CTRLA[0]; however, it is rec-
ommended that a frequency acquisition be initiated by writing
a 1-to-0 transition into CTRLB[5], as explained previously.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2817/ADN2818 compare the
frequency of the incoming data to the incoming reference clock
and return a ratio of the two frequencies to 0.01% (100 ppm).
The accuracy error of the reference clock is added to the accuracy
of the ADN2817/ADN2818 data rate measurement. For example, if
a 100 ppm accuracy reference clock is used, the total accuracy
of the measurement is within 200 ppm.
The reference clock can range from 10 MHz to 200 MHz. The
ADN2817/ADN2818 expects a reference clock between 10 MHz
and 25 MHz by default. If it is between 25 MHz and 50 MHz,
50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user
needs to configure the ADN2817/ADN2818 to use the correct
reference frequency range by setting two bits of the CTRLA
register, CTRLA[7:6]. Using the reference clock to determine
the frequency of the incoming data does not affect the manner
in which the part locks onto data. In this mode, the reference
clock is used only to determine the frequency of the data. For
this reason, the user does not need to know the data rate to use
the reference clock in this manner.
Prior to reading back the data rate using the reference clock, the
CTRLA[7:6] bits must be set to the appropriate frequency range
with respect to the reference clock being used. A fine data rate
readback is then executed as follows:
1. Write a 1 to CTRLA[1]. This enables the fine data rate
measurement capability of the ADN2817/ADN2818.
This bit is level sensitive and does not need to be reset
to perform subsequent frequency measurements.
2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3].
This initiates a new data rate measurement.
3. Read back MISC[2]. If it is 0, the measurement is not
complete. If it is 1, the measurement is complete and
the data rate can be read back on FREQ[22:0]. The time for
a data rate measurement is typically 80 ms.
4. Read back the data rate from the FREQ2[6:0], FREQ1[7:0],
and FREQ0[7:0] registers.
Use the following equation to determine the data rate:
fDATARATE = (FREQ[22..0] × fREFCLK)/2(14 + SEL_RATE)
(1)
where:
FREQ[22:0] is the reading from FREQ2[6:0] (most significant
byte), FREQ1[7:0], and FREQ0[7:0] (least significant byte). See
fDATARATE is the data rate (Mbps).
fREFCLK is the REFCLK frequency (MHz).
SEL_RATE is the setting from CTRLA[7:6].
Table 18.
D22
D21:D17
D16
D15
D14:D9
D8
D7
D6:D1
D0
FREQ2[6:0]
FREQ1[7:0]
FREQ0[7:0]
For example, if the reference clock frequency is 32 MHz, it falls
within the 25 MHz to 50 MHz range; therefore, the CTRLA[7:6]
setting is 01 resulting in SEL_RATE = 1. For this example, the
input data rate is 2.488 Gbps (OC-48). After following Step 1
through Step 4, the value that is read back on FREQ[22:0] =
0x26E010, which is equal to 2.5477 × 106. Plugging this value
into Equation 1 yields
((2.5477 × 106) × (32 × 106))/(2(14 + 1)) = 2.488 Gbps
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The measure-
ment process is reset by writing a 1 followed by a 0 to CTRLB[3].
This initiates a new data rate measurement. Follow Step 2 through
Step 4 to read back the new data rate.
Note that a data rate readback is valid only if LOL is low. If LOL
is high, the data rate readback is invalid.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADN2819 | 制造商:AD 制造商全称:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819ACP-CML | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP Tray 制造商:Rochester Electronics LLC 功能描述:MULTI-RATE 2.7GBPS CDR/ PA LOW POWER I.C - Bulk |
| ADN2819ACP-CML-RL | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R |
| ADN2819ACPZ-CML | 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ADN2819ACPZ-CML1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
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