- 您现在的位置：买卖IC网 > PDF目录9660 > ADN2818ACPZ-RL7 (Analog Devices Inc)IC CLOCK/DATA RECOVERY 32-LFCSP PDF资料下载
参数资料
| 型号： | ADN2818ACPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/40页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-LFCSP |
| 标准包装： | 1,500 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | CML |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.7GHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页当前第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页
Data Sheet
ADN2817/ADN2818
Rev. E | Page 31 of 40
Transmission Lines
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections: PIN, NIN,
CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also
REFCLKP, REFCLKN, if using a high frequency reference clock,
such as 155 MHz). It is also necessary for the PIN/NIN input
traces to be matched in length, and the CLKOUTP, CLKOUTN,
DATAOUTP, and DATAOUTN output traces to be matched
in length to avoid skew between the differential traces.
All high speed CML outputs (CLKOUTP, CLKOUTN, DATAOUTP,
and DATAOUTN) require 100 Ω back termination chip resis-
tors connected between the output pin and VCC. Place these
resistors as close as possible to the output pins. These 100 Ω
resistors are in parallel with on-chip 100 Ω termination resistors
to create a 50 Ω back termination (see Figure 37).
The high speed inputs (PIN and NIN) are internally terminated
with 50 Ω to an internal reference voltage (see Figure 38). A 0.1 μF
capacitor is recommended between VREF, Pin 3, and GND to
provide an ac ground for the inputs.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
50
VTERM
50
0.1F
100
VCC
100
VCC
ADN2817/ADN2818
0
60
01
-02
6
Figure 37. Typical ADN2817/ADN2818 Applications Circuit
50
2.5V
ADN2817/ADN2818
VCC
TIA
CIN
PIN
NIN
3k
VREF
0.1F
TIA
06
001
-0
27
Figure 38. ADN2817/ADN2818 AC-Coupled Input Configuration
Soldering Guidelines for Lead Frame Chip Scale Package
The lands on the 32-lead LFCSP are rectangular. The printed
circuit board pad for these should be 0.1 mm longer than the
package land length, and 0.05 mm wider than the package land
width. Center the land on the pad to ensure that the solder joint
size is maximized. The bottom of the lead frame chip scale package
has a central exposed pad. The pad on the printed circuit board
should be at least as large as this exposed pad. The user must
connect the exposed pad to VEE using plugged vias to prevent
solder from leaking through the vias during reflow. This ensures a
solid connection from the exposed pad to VEE.
Choosing AC Coupling Capacitors
AC coupling capacitors at the input (PIN, NIN) and output
(DATAOUTP, DATAOUTN) of the ADN2817/ADN2818
must be chosen such that the device works properly over the
full range of data rates used in the application. When choosing
the capacitors, the time constant formed with the two 50 Ω
resistors in the signal path must be considered. When a large
number of consecutive identical digits (CIDs) are applied, the
capacitor voltage can droop due to baseline wander (see Figure 39),
causing pattern dependent jitter (PDJ).
The user must determine how much droop is tolerable and choose
an ac coupling capacitor based on that amount of droop. The
amount of PDJ can then be approximated based on the capacitor
selection. The actual capacitor value selection may require some
trade-offs between droop and PDJ.
For example, assuming that 2% droop can be tolerated, the
maximum differential droop is 4%. Normalizing to peak-to-
peak voltage,
Droop = Δ V = 0.04 V = 0.5 V p-p (1 e–t/τ) ; therefore, τ = 12t
where:
τ is the RC time constant (C is the ac coupling capacitor, and
R = 100 Ω seen by C).
t is the total discharge time, which is equal to n.
n is the number of CIDs.
T is the bit period.
Calculate the capacitor value by combining the equations
for τ and t.
C = 12nT/R
When the capacitor value is selected, the PDJ can be
approximated as
PDJps p-p = 0.5tr(1 e(nT/RC))/0.6
where:
PDJps p-p is the amount of pattern-dependent jitter allowed;
<0.01 UI p-p typical.
tr is the rise time, which is equal to 0.22/BW, where BW ≈ 0.7
(bit rate).
Note that this expression for tr is accurate only for the inputs.
The output rise time for the ADN2817/ADN2818 is ~100 ps
regardless of data rate.
相关PDF资料 |
PDF描述 |
|---|---|
| MS27472E24B35SA | CONN RCPT 128POS WALL MNT W/SCKT |
| MS27468T25B19P | CONN RCPT 19POS JAM NUT W/PINS |
| SY87701LZG | IC CLOCK/DATA RECOVERY 28-SOIC |
| VI-21Z-MV-F2 | CONVERTER MOD DC/DC 2V 60W |
| SY87721LHY TR | IC CLOCK/DATA RECOVERY 64-TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADN2819 | 制造商:AD 制造商全称:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819ACP-CML | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP Tray 制造商:Rochester Electronics LLC 功能描述:MULTI-RATE 2.7GBPS CDR/ PA LOW POWER I.C - Bulk |
| ADN2819ACP-CML-RL | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R |
| ADN2819ACPZ-CML | 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ADN2819ACPZ-CML1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
发布紧急采购，3分钟左右您将得到回复。