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| 型号： | ADP1048ARQZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/84页 |
| 文件大小： | 0K |
| 描述： | IC DGTL PFC CTRLR 24QSOP |
| 标准包装： | 1 |
| 模式： | 平均电流 |
| 频率 - 开关： | 30kHz ~ 400kHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 标准包装 |
| 其它名称： | ADP1048ARQZ-R7DKR |
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ADP1047/ADP1048
CURRENT BALANCING (IBAL PIN, ADP1048 ONLY)
The ADP1048 has a dedicated circuit to maintain current balance
in each interleaved phase when operating in interleaved PFC
topology. This ensures that each interleaved phase provides equal
power regardless of the tolerance of the inductor and the boost
switch driving circuitry.
The input is through the IBAL pin specifically provided for the
flowing in both switches of the interleaved PFC topology and
stores this information. It compensates the PWM signals,
ensuring equal current flow to balance the current between
interleaved phases. Several switching cycles are required for
the circuit to operate effectively. The current balance settings
Data Sheet
The voltage sense can be calibrated digitally to remove any
be performed in the production environment; the settings
Input Voltage Sensing (VAC Pin)
The VAC pin is used for the monitoring and protection of the
rectified power supply input voltage. The sense point on the
power rail requires an external resistor divider to bring the signal
within the operating input range of the ADC (0 V to 1.6 V).
This scaled-down signal is fed into a high speed Σ-Δ ADC.
The output of the Σ-Δ ADC goes to the digital filter and is used
for the following purposes:
are programmed in Register 0xFE43 and Register 0xFE95.
?
?
The output is decimated at the switching frequency for the
control loop. The effective number of bits (ENOB) is >7
when the current loop bandwidth is 10 kHz; the ENOB
is >10 when the current loop bandwidth is 1 kHz.
The 11-bit result is calculated and updated at each half line
cycle for high accuracy input voltage and power monitoring.
IBAL
PGND
0° TO 180°
Output Voltage Sensing (VFB Pin)
The VFB pin is used for the control, monitoring, and protection
ADC
+
K
of the output voltage. This voltage is the main feedback loop for
the power supply control loop. The sense point on the power rail
ADP1048
–
ADC
180° TO 360°
PWM
OUTPUT OF PFC
CURRENT LOOP
requires an external resistor divider to bring the signal within the
operating input range of the ADC (0 V to 1.6 V). This scaled-
down signal is fed into a high speed Σ-Δ ADC.
The output of the Σ-Δ ADC goes to the digital filter and is used
for the following purposes:
PWM PWM2
Figure 10. Current Balancing (IBAL) for the ADP1048
VOLTAGE SENSE
Voltage sensing is used for the control, protection, and monitor-
ing of the PFC stage. Input and output voltages are sensed using
dedicated ADCs and references (see Figure 11).
?
?
The 11-bit result is used at each half line cycle for the
normal control loop to control the value of the output
voltage.
The 10-bit, 1.5 kHz update rate is used for the fast voltage
control loop to control the value of the output voltage
during large transients.
V REC
V OUT
To reduce the current distortion from the output voltage feed-
back, a prefilter is implemented before the voltage loop filter.
The prefilter detects the zero-crossing point of the input voltage
to identify the half input line cycle. The prefilter then performs
an averaging function for the sampled VFB signal during this
half line cycle. In this way, the fundamental frequency of the
output bulk voltage ripple and its harmonics are significantly
VAC
PGND
+ –
VFB
+ –
OVP
+ –
attenuated.
DAC
ADC
ADC
OLP
OVP
7-BIT
11-BIT
11-BIT
ADP1047/ADP1048
Figure 11. Typical Voltage Sense Configuration
Rev. 0 | Page 14 of 84
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