参数资料
型号: ADP1048ARQZ-R7
厂商: Analog Devices Inc
文件页数: 32/84页
文件大小: 0K
描述: IC DGTL PFC CTRLR 24QSOP
标准包装: 1
模式: 平均电流
频率 - 开关: 30kHz ~ 400kHz
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
供应商设备封装: 24-QSOP
包装: 标准包装
其它名称: ADP1048ARQZ-R7DKR
ADP1047/ADP1048
BRIDGELESS BOOST OPERATION ( ADP1048 ONLY)
The bridgeless boost configuration allows removal of the con-
duction losses caused by the input bridge of the PFC converter.
In this configuration, it is necessary to drive the two power
MOSFETs separately to achieve the highest efficiency. The
ADP1048 can provide such signals. The IBAL pin is used to
detect the ac line phase and zero crossings. Note that the maxi-
mum rating on the IBAL pin is VDD + 0.3 V; therefore, a clamp
circuit must be connected to the IBAL pin.
Data Sheet
During the positive ac line phase, only one boost stage is effec-
tively working. The second one is passive, and the current flows in
Q2 from the source to the drain. Turning the Q2 FET fully on
during this phase allows conduction losses in Q2 to be minimized.
When the ac line phase becomes negative, the roles of Q1 and Q2
are reversed, and Q2 actively switches while Q1 is always on. The
phase information is detected from the ac line via the IBAL pin.
During the soft start phase, both FETs are switching as a precau-
tionary measure; the same happens when the phase information
on the IBAL pin becomes corrupted or inaccurate.
AC
INPUT
RELAY
T3
V OUT
V REC
T1
Q1
3.3V
T2
Q2
BULK
CAPACITOR
1
2
3
4
AGND
VAC
VFB
OVP
VDD 24
RES 23
RTD 22
ADD 21
5
6
7
8
PGND
ILIM
IBAL
CS–
SDA 20
SCL 19
SYNC 18
INRUSH 17
PMBus
T1 + T2 + T3
9
10
11
12
CS+
DGND
PSON
VCORE
PGOOD 16
AC_OK 15
PWM2 14
PWM 13
ADP1048
Figure 33. Schematic of Bridgeless PFC Circuit with the ADP1048
VAC
IBAL PIN
PWM
PWM2
Figure 34. Bridgeless Boost Operation
Rev. 0 | Page 32 of 84
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