参数资料
型号: ADP1048ARQZ-R7
厂商: Analog Devices Inc
文件页数: 46/84页
文件大小: 0K
描述: IC DGTL PFC CTRLR 24QSOP
标准包装: 1
模式: 平均电流
频率 - 开关: 30kHz ~ 400kHz
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
供应商设备封装: 24-QSOP
包装: 标准包装
其它名称: ADP1048ARQZ-R7DKR
ADP1047/ADP1048
Data Sheet
RESTORE_USER_ALL COMMAND
Code 0x16, send byte, no data. This command downloads the stored user settings from EEPROM into operating memory.
CAPABILITY REGISTER
This register allows host systems to determine the capabilities of the PMBus device.
Table 20. Register 0x19—CAPABILITY
Bits
7
Bit Name
Packet error
R/W
R
Description
Always reads as 0. Packet error checking (PEC) is not supported.
checking
[6:5]
4
[3:0]
Maximum bus
speed
SMBALERT#
RSVD
R
R
R
Return the device PMBus speed capability. These bits are hardcoded to a value of 01 (use the
400 kHz maximum bus speed).
Always reads as 0. SMBALERT# pin and SMBus alert response protocol not supported.
Reserved.
VOUT_MODE REGISTER
This register sets and reads the format (linear, VID, direct) and exponents for VOUT related commands.
Table 21. Register 0x20—VOUT_MODE
Bits
[7:5]
[4:3]
[2:0]
Bit Name
Mode
RSVD
Exponent
R/W
R
R
R/W
Description
Return the output voltage data format. This bit is hardcoded to use linear format.
Reserved.
Specify the exponent (N) used in VOUT linear mode format (X = Y × 2 N ). The exponent is in twos
complement format.
VOUT_COMMAND REGISTER
This register sets VOUT to the configured value.
Table 22. Register 0x21—VOUT_COMMAND
Bits
[15:12]
[11:0]
Bit Name
RSVD
Mantissa
R/W
R
R/W
Description
Reserved. Always reads as 0000.
Mantissa (Y[11:0]) used in VOUT linear mode format (X = Y × 2 N ).
VOUT_SCALE_LOOP REGISTER
This register sets the K factor = VADC/VOUT.
Table 23. Register 0x29—VOUT_SCALE_LOOP
Bits
[15:11]
10
[9:0]
Bit Name
Exponent
RSVD
Mantissa
R/W
R/W
R
R/W
Description
Write the exponent (N) in twos complement format for K = Y × 2 N .
Always reads as 0.
Mantissa (Y[9:0]) used in K linear mode format (K = Y × 2 N ).
Rev. 0 | Page 46 of 84
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