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| 型号： | ADP1048ARQZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/84页 |
| 文件大小： | 0K |
| 描述： | IC DGTL PFC CTRLR 24QSOP |
| 标准包装： | 1 |
| 模式： | 平均电流 |
| 频率 - 开关： | 30kHz ~ 400kHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 标准包装 |
| 其它名称： | ADP1048ARQZ-R7DKR |
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ADP1047/ADP1048
Fast Loop Mode
During transients, a fast loop mode is enabled to allow for faster
loop responses. Typical timing can be seen in Figure 15. The
fast loop mode has separate settings and can be programmed to
respond quickly to load transients. The user can disable the fast
VFB
VFB ERROR
FAST LOOP
Data Sheet
loop mode if it is not required by the application.
VFB FAST ERROR
V REC
NORMAL FILTER
@ 100Hz
I LOAD
PROGRAMMABLE
FAST FILTER
@ 1.5kHz
Figure 16. Fast Loop Operation
V OUT
PROGRAM-
RANGE
Based on the requirements of the application, the user can enable
or disable the fast loop mode by programming Register 0xFE24.
MABLE
DELAY
(0 TO 7
HALF LINE
CYCLES)
FAST LOOP
Figure 15. Fast Loop for Transient Response Improvement
When fast loop mode is enabled and the feedback output voltage
is out of range from the desired reference value (programmable
band of 1.5%, 3%, 6%, or 12%, set in Register 0xFE24), the
To ensure a smooth transition, the ADP1047 / ADP1048 switch
from the regular filter to the fast loop filter at the zero crossing
of the rectified input voltage. When the output voltage returns
to regulation within the programmed band, the controller
switches back (after a programmable delay of 0 to 7 half line
cycles) to the normal loop at the next zero crossing of the
rectified input voltage.
If the output voltage does not return to regulation within the
programmed band after a fixed time of 630 ms, the control loop
automatically switches back to the normal loop.
In the normal compensation loop, the sampling frequency of
the output voltage is the same as the ripple oscillation frequency
(which is commonly 100 Hz or 120 Hz).
During fast loop operation, the feedback voltage is sampled
at 1.5 kHz, and the fast filter is applied to regulate the output
voltage. The output voltage is averaged and decimated at
1.5 kHz (see Figure 16).
It is recommended that fast loop mode be enabled for the
mode settings are also used during soft start, even when the fast
loop is disabled.
PULSE-WIDTH MODULATION
The ADP1047 / ADP1048 can implement either leading edge or
trailing edge modulation. Trailing edge modulation is the more
popular modulation scheme. Using trailing edge modulation,
the rms ripple current in the bulk capacitors can be reduced
when used with downstream converter synchronization. It is
recommended that the Analog Devices, Inc., GUI software be
used to program PWM (see the Software GUI section).
DUTY CYCLE MINIMUM/MAXIMUM LIMITS
The ADP1047 / ADP1048 allow the user to program the mini-
mum off time and the minimum on time for the PWM outputs
separately, thereby allowing the minimum and maximum duty
cycles to be set.
The minimum off time represents the minimum time that the
PWM is low during each switching cycle. It can be programmed
from 40 ns to 1.2 μs in steps of 80 ns using Register 0xFE15,
Bits[3:0]. In this way, the maximum duty cycle can be clamped
between 96% and 99.8% at the minimum frequency and
between 48.8% and 96.8% at the maximum frequency.
The minimum on time is the smallest PWM pulse that the mod-
ulator generates on the PWM output. It can be programmed
from 0 ns to 1200 ns in steps of 80 ns using Register 0xFE15,
Bits[7:4].
AUXILIARY PWM OUTPUT ( ADP1047 ONLY)
For the ADP1047 , the PWM2 pin is the output for the auxiliary
PWM, which can be independent of the main PWM output.
PWM2 can be used as the control signal for auxiliary switching
in the zero-voltage transition soft-switched PFC boost circuit.
Rev. 0 | Page 18 of 84
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