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| 型号： | ADZS-BF561-EZLITE |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/64页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ADSP-BF561 |
| 产品培训模块： | Interfacing AV Converters to Blackfin Processors Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 特色产品： | Blackfin? BF50x Series Processors |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | DSP |
| 适用于相关产品： | ADSP-BF561 |
| 所含物品： | 评估板、软件和说明文档 |
| 配用： | ADZS-USBLAN-EZEXT-ND - BOARD DAUGHTER EXTENDED USB-LAN ADZS-BFFPGA-EZEXT-ND - BOARD EVAL FPGA BLACKFIN EXTENDR ADZS-BF-EZEXT-1-ND - BOARD DAUGHTER ADSP-BF533/561KIT |
| 相关产品： | ADSP-BF561SKBCZ-6V-ND - IC DSP 32BIT 600MHZ 256CSPBGA ADSP-BF561SKBCZ-5V-ND - IC DSP 32BIT 500MHZ 256CSPBGA ADSP-BF561SKBCZ-5A-ND - IC DSP CTLR 32BIT BKFN 256CSPBGA ADSP-BF561SKBCZ-6A-ND - IC DSP CTRLR 32B 600MHZ 256CPBGA ADSP-BF561SBBCZ-5A-ND - IC DSP CTRLR 32B 500MHZ 256CPBGA ADSP-BF561SBBZ500-ND - IC PROCESSOR 500MHZ 297-PBGA ADSP-BF561SBBZ600-ND - IC DSP 32BIT 600MHZ 297-BGA ADSP-BF561SKBZ600-ND - IC DSP 32BIT 600MHZ 297PBGA ADSP-BF561SKBZ500-ND - IC DSP 32BIT 500MHZ 297PBGA ADSP-BF561SKB600-ND - IC DSP CTRLR 32BIT 600MHZ 297BGA 更多... |
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ADSP-BF561
board. All internal and I/O power supplies should be well
bypassed with bypass capacitors placed as close to the
ADSP-BF561 processors as possible.
For further details on the on-chip voltage regulator and related
board design guidelines, see the Switching Regulator Design
Considerations for ADSP-BF533 Blackfin Processors (EE-228)
log.com )—use site search on “EE-228”.
CLKOUT
EN
Blackfin
TO PLL CIRCUITRY
700 O
CLOCK SIGNALS
The ADSP-BF561 processor can be clocked by an external crys-
tal, a sine wave input, or a buffered, shaped clock derived from
CLKIN
XTAL
0 O *
V DDEXT
1M O
an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
18pF*
18pF*
FOR OVERTONE
OPERATION ONLY
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF561 processor includes an
on-chip oscillator circuit, an external crystal may be used. For
fundamental frequency operation, use the circuit shown in
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
Figure 5. External Crystal Connections
processor-grade crystal is connected across the CLKIN and
XTAL pins. The on-chip resistance between CLKIN and the
XTAL pin is in the 500 k Ω range. Further parallel resistors are
typically not recommended. The two capacitors and the series
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
resistor shown in Figure 5 fine tune the phase and amplitude of
÷ 1, 2, 4, 8
CCLK
the sine frequency. The capacitor and resistor values shown in
dent upon the crystal manufacturer’s load capacitance
CLKIN
PLL
0.5 u to 64 u
VCO
÷ 1 to 15
SCLK
recommendations and the physical PCB layout. The resistor
value depends on the drive level specified by the crystal manu-
Signal Name
Divider Ratio
facturer. System designs should verify the customized values
based on careful investigation on multiple devices over the
allowed temperature range.
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
As shown in Figure 6 , the core clock (CCLK) and system
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user-programmable 0.5 × to 64 × multiplica-
tion factor. The default multiplier is 10 × , but it can be modified
SCLK d CCLK
SCLK d 133 MHz
Figure 6. Frequency Modification Methods
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 5 illustrates typical system clock ratios.
Table 5. Example System Clock Ratios
Example Frequency
Ratios (MHz)
by a software instruction sequence. On the fly frequency
changes can be effected by simply writing to the PLL_DIV
register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0
0001
0110
1010
VCO/SCLK
1:1
6:1
10:1
VCO
100
300
500
SCLK
100
50
50
SSEL3–0 bits of the PLL_DIV register. The values programmed
The maximum frequency of the system clock is f SCLK . Note that
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f SCLK . The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
Rev. E |
Page 13 of 64 |
September 2009
相关PDF资料 |
PDF描述 |
|---|---|
| ADZS-BF592-EZLITE | KIT EVAL EZ LITE ADZS-BF592 |
| ADZS-BF609-EZBRD | KIT EVAL EZ-BOARD ADSP-BF60X |
| ADZS-HPUSB-ICE | TOOL EMULATOR USB HP CROSSCORE |
| ADZS-ICE-100B | EMULATOR BLACKFIN |
| AK-Y1301 | CABLE SCSI-3 EXTENSION 68CONDUCT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADZS-BF561-MMSKIT | 功能描述:KIT STARTER MULTIMEDIA BF561 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 标准包装:1 系列:PICDEM™ 类型:MCU 适用于相关产品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，线缆，元件，CD，PICkit 编程器 产品目录页面:659 (CN2011-ZH PDF) |
| ADZS-BF561-MMSKIT | 制造商:Analog Devices 功能描述:MEDIA KIT ((NW)) |
| ADZS-BF592-EZLITE | 功能描述:KIT EVAL EZ LITE ADZS-BF592 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| ADZS-BF592-EZLITE | 制造商:Analog Devices 功能描述:ADZS-BF592-EZLITE |
| ADZS-BF608-EZLITE | 制造商:Analog Devices 功能描述:DIGITAL SIGNAL PROCESSOR - DEVELOPMENT TOOL |
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