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参数资料
型号： ADZS-BF561-EZLITE
厂商： Analog Devices Inc
文件页数： 14/64页
文件大小： 0K
描述： BOARD EVAL ADSP-BF561
产品培训模块： Interfacing AV Converters to Blackfin Processors
Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
特色产品： Blackfin? BF50x Series Processors
标准包装： 1
系列： Blackfin®
类型： DSP
适用于相关产品： ADSP-BF561
所含物品： 评估板、软件和说明文档
配用： ADZS-USBLAN-EZEXT-ND - BOARD DAUGHTER EXTENDED USB-LAN
ADZS-BFFPGA-EZEXT-ND - BOARD EVAL FPGA BLACKFIN EXTENDR
ADZS-BF-EZEXT-1-ND - BOARD DAUGHTER ADSP-BF533/561KIT
相关产品： ADSP-BF561SKBCZ-6V-ND - IC DSP 32BIT 600MHZ 256CSPBGA
ADSP-BF561SKBCZ-5V-ND - IC DSP 32BIT 500MHZ 256CSPBGA
ADSP-BF561SKBCZ-5A-ND - IC DSP CTLR 32BIT BKFN 256CSPBGA
ADSP-BF561SKBCZ-6A-ND - IC DSP CTRLR 32B 600MHZ 256CPBGA
ADSP-BF561SBBCZ-5A-ND - IC DSP CTRLR 32B 500MHZ 256CPBGA
ADSP-BF561SBBZ500-ND - IC PROCESSOR 500MHZ 297-PBGA
ADSP-BF561SBBZ600-ND - IC DSP 32BIT 600MHZ 297-BGA
ADSP-BF561SKBZ600-ND - IC DSP 32BIT 600MHZ 297PBGA
ADSP-BF561SKBZ500-ND - IC DSP 32BIT 500MHZ 297PBGA
ADSP-BF561SKB600-ND - IC DSP CTRLR 32BIT 600MHZ 297BGA
更多...
ADSP-BF561 
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 6 . This programmable core clock capability is useful for
fast core frequency modifications.
Table 6. Core Clock Ratios
Example Frequency
All configuration settings are set for the slowest device pos-
sible (3-cycle hold time; 15-cycle R/W access times; 4-cycle
setup).
? Boot from SPI host device – The Blackfin processor oper-
ates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
off the host device from transmitting while the boot ROM
is busy, the Blackfin processor asserts a GPIO pin, called
Signal Name
CSEL1–0
00
01
10
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
Ratios (MHz)
VCO CCLK
500 500
500 250
200 50
host wait (HWAIT), to signal the host device not to send
any more bytes until the flag is deasserted. The flag is cho-
sen by the user and this information is transferred to the
Blackfin processor via bits 10:5 of the FLAG header.
? Boot from SPI serial EEPROM (16-, 24-bit addressable) –
The SPI uses the PF2 output pin to select a single SPI
11
8:1
200
25
EPROM device, submits a read command at address
0x0000, and begins clocking data into the beginning of L1
The maximum PLL clock time when a change is programmed
via the PLL_CTL register is 40 μs. The maximum time to change
the internal voltage via the internal voltage regulator is also
40 μs. The reset value for the PLL_LOCKCNT register is 0x200.
This value should be programmed to ensure a 40 μs wakeup
time when either the voltage is changed or a new MSEL value is
programmed. The value should be programmed to ensure an
80 μs wakeup time when both voltage and the MSEL value are
changed. The time base for the PLL_LOCKCNT register is the
period of CLKIN.
BOOTING MODES
The ADSP-BF561 has three mechanisms (listed in Table 7 ) for
automatically loading internal L1 instruction memory, L2, or
external memory after a reset. A fourth mode is provided to exe-
cute from external memory, bypassing the boot sequence.
Table 7. Booting Modes
BMODE1 –0 Description
instruction memory. A 16-, 24-bit addressable SPI-compat-
ible EPROM must be used.
For each of the boot modes, a boot loading protocol is used to
transfer program and data blocks from an external memory
device to their specified memory locations. Multiple memory
blocks may be loaded by any boot sequence. Once all blocks are
loaded, Core A program execution commences from the start of
L1 instruction SRAM (0xFFA0 0000). Core B remains in a held-
off state until Bit 5 of SICA_SYSCR is cleared by Core A. After
that, Core B will start execution at address 0xFF60 0000.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax that was designed for ease of coding
and readability. The instructions have been specifically tuned to
00
01
10
11
Execute from 16-bit external memory
(Bypass Boot ROM)
Boot from 8-bit/16-bit flash
Boot from SPI host slave mode
Boot from SPI serial EEPROM
(16-, 24-bit address range)
provide a flexible, densely encoded instruction set that compiles
to a very small final memory size. The instruction set also pro-
vides fully featured multifunction instructions that allow the
programmer to use many of the processor core resources in a
single instruction. Coupled with many features more often seen
on microcontrollers, this instruction set is very efficient when
compiling C and C++ source code. In addition, the architecture
supports both a user (algorithm/application code) and a super-
The BMODE pins of the reset configuration register, sampled
during power-on resets and software initiated resets, implement
the following modes:
? Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time,
15-cycle R/W access times, 4-cycle setup). Note that, in
bypass mode, only Core A can execute instructions from
external memory.
? Boot from 8-bit/16-bit external flash memory – The
8-bit/16-bit flash boot routine located in boot ROM mem-
ory space is set up using Asynchronous Memory Bank 0.
visor (O/S kernel, device drivers, debuggers, ISRs) mode of
operation—allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
? Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.
? A multi-issue load/store modified Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU plus
two load/store plus two pointer updates per cycle.
Rev. E |
Page 14 of 64 |
September 2009
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ADZS-BF561-MMSKIT 功能描述:KIT STARTER MULTIMEDIA BF561 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 标准包装:1 系列:PICDEM™ 类型:MCU 适用于相关产品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，线缆，元件，CD，PICkit 编程器 产品目录页面:659 (CN2011-ZH PDF)
ADZS-BF561-MMSKIT 制造商:Analog Devices 功能描述:MEDIA KIT ((NW))
ADZS-BF592-EZLITE 功能描述:KIT EVAL EZ LITE ADZS-BF592 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
ADZS-BF592-EZLITE 制造商:Analog Devices 功能描述:ADZS-BF592-EZLITE
ADZS-BF608-EZLITE 制造商:Analog Devices 功能描述:DIGITAL SIGNAL PROCESSOR - DEVELOPMENT TOOL
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