参数资料
型号: ADZS-BF561-EZLITE
厂商: Analog Devices Inc
文件页数: 4/64页
文件大小: 0K
描述: BOARD EVAL ADSP-BF561
产品培训模块: Interfacing AV Converters to Blackfin Processors
Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
特色产品: Blackfin? BF50x Series Processors
标准包装: 1
系列: Blackfin®
类型: DSP
适用于相关产品: ADSP-BF561
所含物品: 评估板、软件和说明文档
配用: ADZS-USBLAN-EZEXT-ND - BOARD DAUGHTER EXTENDED USB-LAN
ADZS-BFFPGA-EZEXT-ND - BOARD EVAL FPGA BLACKFIN EXTENDR
ADZS-BF-EZEXT-1-ND - BOARD DAUGHTER ADSP-BF533/561KIT
相关产品: ADSP-BF561SKBCZ-6V-ND - IC DSP 32BIT 600MHZ 256CSPBGA
ADSP-BF561SKBCZ-5V-ND - IC DSP 32BIT 500MHZ 256CSPBGA
ADSP-BF561SKBCZ-5A-ND - IC DSP CTLR 32BIT BKFN 256CSPBGA
ADSP-BF561SKBCZ-6A-ND - IC DSP CTRLR 32B 600MHZ 256CPBGA
ADSP-BF561SBBCZ-5A-ND - IC DSP CTRLR 32B 500MHZ 256CPBGA
ADSP-BF561SBBZ500-ND - IC PROCESSOR 500MHZ 297-PBGA
ADSP-BF561SBBZ600-ND - IC DSP 32BIT 600MHZ 297-BGA
ADSP-BF561SKBZ600-ND - IC DSP 32BIT 600MHZ 297PBGA
ADSP-BF561SKBZ500-ND - IC DSP 32BIT 500MHZ 297PBGA
ADSP-BF561SKB600-ND - IC DSP CTRLR 32BIT 600MHZ 297BGA
更多...
ADSP-BF561 
ADDRESS ARITHMETIC UNIT
SP
I3
I2
L3
L2
B3
B2
M3
M2
FP
P5
I1
I0
L1
L0
B1
B0
M1
M0
DAG1
DAG0
P4
P3
DA1
DA0
SD
32
32
32
32
RAB
P2
P1
P0
32
PREG
LD1
LD0
32
32
32
32
ASTAT
SEQUENCER
R7.H
R6.H
R7.L
R6.L
R5.H
R4.H
R3.H
R5.L
R4.L
R3.L
8
16
8
8
16
8
ALIGN
R2.H
R1.H
R2.L
R1.L
BARREL
DECODE
R0.H
R0.L
SHIFTER
A0
40
40
40
40
A1
LOOP BUFFER
CONTROL
UNIT
32
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
MEMORY ARCHITECTURE
The ADSP-BF561 views memory as a single unified 4G byte
address space, using 32-bit addresses. All resources including
internal memory, external memory, and I/O control registers
occupy separate sections of this common address space. The
memory portions of this address space are arranged in a hierar-
chical structure to provide a good cost/performance balance of
some very fast, low latency memory as cache or SRAM very
close to the processor, and larger, lower cost and performance
memory systems farther away from the processor. The
ADSP-BF561 memory map is shown in Figure 3 .
The L1 memory system in each core is the highest performance
memory available to each Blackfin core. The L2 memory pro-
vides additional capacity with lower performance. Lastly, the
off-chip memory system, accessed through the External Bus
Interface Unit (EBIU), provides expansion with SDRAM, flash
memory, and SRAM, optionally accessing more than
768M bytes of physical memory. The memory DMA controllers
provide high bandwidth data movement capability. They can
perform block transfers of code or data between the internal
L1/L2 memories and the external memory spaces.
Internal (On-Chip) Memory
The ADSP-BF561 has four blocks of on-chip memory providing
high bandwidth access to the core.
The first is the L1 instruction memory of each Blackfin core
consisting of 16K bytes of four-way set-associative cache mem-
ory and 16K bytes of SRAM. The cache memory may also be
configured as an SRAM. This memory is accessed at full proces-
sor speed. When configured as SRAM, each of the two 16K
banks of memory is broken into 4K sub-banks which can be
independently accessed by the processor and DMA.
The second on-chip memory block is the L1 data memory of
each Blackfin core which consists of four banks of 16K bytes
each. Two of the L1 data memory banks can be configured as
one way of a two-way set-associative cache or as an SRAM. The
other two banks are configured as SRAM. All banks are accessed
at full processor speed. When configured as SRAM, each of the
four 16K banks of memory is broken into 4K sub-banks which
can be independently accessed by the processor and DMA.
The third memory block associated with each core is a 4K byte
scratchpad SRAM which runs at the same speed as the L1 mem-
ories, but is only accessible as data SRAM (it cannot be
configured as cache memory and is not accessible via DMA).
Rev. E |
Page 4 of 64 |
September 2009
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ADZS-BF561-MMSKIT 制造商:Analog Devices 功能描述:MEDIA KIT ((NW))
ADZS-BF592-EZLITE 功能描述:KIT EVAL EZ LITE ADZS-BF592 RoHS:是 类别:编程器,开发系统 >> 通用嵌入式开发板和套件(MCU、DSP、FPGA、CPLD等) 系列:Blackfin® 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板,软件,4x4 键盘,光学拨轮,QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
ADZS-BF592-EZLITE 制造商:Analog Devices 功能描述:ADZS-BF592-EZLITE
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