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| 型号： | ADZS-BF561-EZLITE |
| 厂商： | Analog Devices Inc |
| 文件页数： | 43/64页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ADSP-BF561 |
| 产品培训模块： | Interfacing AV Converters to Blackfin Processors Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 特色产品： | Blackfin? BF50x Series Processors |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | DSP |
| 适用于相关产品： | ADSP-BF561 |
| 所含物品： | 评估板、软件和说明文档 |
| 配用： | ADZS-USBLAN-EZEXT-ND - BOARD DAUGHTER EXTENDED USB-LAN ADZS-BFFPGA-EZEXT-ND - BOARD EVAL FPGA BLACKFIN EXTENDR ADZS-BF-EZEXT-1-ND - BOARD DAUGHTER ADSP-BF533/561KIT |
| 相关产品： | ADSP-BF561SKBCZ-6V-ND - IC DSP 32BIT 600MHZ 256CSPBGA ADSP-BF561SKBCZ-5V-ND - IC DSP 32BIT 500MHZ 256CSPBGA ADSP-BF561SKBCZ-5A-ND - IC DSP CTLR 32BIT BKFN 256CSPBGA ADSP-BF561SKBCZ-6A-ND - IC DSP CTRLR 32B 600MHZ 256CPBGA ADSP-BF561SBBCZ-5A-ND - IC DSP CTRLR 32B 500MHZ 256CPBGA ADSP-BF561SBBZ500-ND - IC PROCESSOR 500MHZ 297-PBGA ADSP-BF561SBBZ600-ND - IC DSP 32BIT 600MHZ 297-BGA ADSP-BF561SKBZ600-ND - IC DSP 32BIT 600MHZ 297PBGA ADSP-BF561SKBZ500-ND - IC DSP 32BIT 500MHZ 297PBGA ADSP-BF561SKB600-ND - IC DSP CTRLR 32BIT 600MHZ 297BGA 更多... |
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ADSP-BF561
The time for the voltage on the bus to decay by Δ V is dependent
on the capacitive load C L and the load current I L . This decay time
can be approximated by the equation:
14
12
t DECAY = ( C L Δ V ) ? I L
The time t DECAY is calculated with test loads C L and I L , and with
Δ V equal to 0.5 V for V DDEXT (nominal) = 2.5 V/3.3 V.
The time t DIS _ MEASURED is the interval from when the reference sig-
nal switches, to when the output voltage decays Δ V from the
measured output high or output low voltage.
Example System Hold Time Calculation
10
8
6
4
2
RISE TIME
FALL TIME
To determine the data output hold time in a particular system,
first calculate t DECAY using the equation given above. Choose Δ V
0
0
50
100 150
LOAD CAPACITANCE (pF)
200
250
to be the difference between the ADSP-BF561 processor’s out-
put voltage and the input threshold for the device requiring the
hold time. C L is the total bus capacitance (per data line), and I L is
the total leakage or three-state current (per data line). The hold
time will be t DECAY plus the various output disable times as speci-
fied in the Timing Specifications on Page 23 (for example t DSDAT
REFERENCE
Figure 40. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at V DDEXT (min)
12
10
RISE TIME
8
FALL TIME
6
SIGNAL
4
t DIS_MEASURED
t ENA_MEASURED
t DIS
t ENA
2
V OH
(MEASURED)
V OL
(MEASURED)
V OH (MEASURED)
V OL (MEASURED) +
V
V
V OH (MEASURED)
V TRIP (HIGH)
V TRIP (LOW)
V OL (MEASURED)
0
0
50
100 150
LOAD CAPACITANCE (pF)
200
250
t DECAY
OUTPUT STOPS DRIVING
t TRIP
OUTPUT STARTS DRIVING
Figure 41. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at V DDEXT (max)
12
HIGH IMPEDANCE STATE
Figure 38. Output Enable/Disable
Capacitive Loading
10
8
RISE TIME
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 39 ). V LOAD is 1.5 V for V DDEXT (nomi-
nal) = 2.5 V/3.3 V. Figure 40 through Figure 47 on Page 44 show
how output rise time varies with capacitance. The delay and
hold specifications given should be derated by a factor derived
from these figures. The graphs in these figures may not be linear
outside the ranges shown.
6
4
2
FALL TIME
TO
OUTPUT
50 O
V LOAD
0
0
50
100 150
LOAD CAPACITANCE (pF)
200
250
PIN
30pF
Figure 39. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 42. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver B at V DDEXT (min)
Rev. E |
Page 43 of 64 |
September 2009
相关PDF资料 |
PDF描述 |
|---|---|
| ADZS-BF592-EZLITE | KIT EVAL EZ LITE ADZS-BF592 |
| ADZS-BF609-EZBRD | KIT EVAL EZ-BOARD ADSP-BF60X |
| ADZS-HPUSB-ICE | TOOL EMULATOR USB HP CROSSCORE |
| ADZS-ICE-100B | EMULATOR BLACKFIN |
| AK-Y1301 | CABLE SCSI-3 EXTENSION 68CONDUCT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADZS-BF561-MMSKIT | 功能描述:KIT STARTER MULTIMEDIA BF561 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 标准包装:1 系列:PICDEM™ 类型:MCU 适用于相关产品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，线缆，元件，CD，PICkit 编程器 产品目录页面:659 (CN2011-ZH PDF) |
| ADZS-BF561-MMSKIT | 制造商:Analog Devices 功能描述:MEDIA KIT ((NW)) |
| ADZS-BF592-EZLITE | 功能描述:KIT EVAL EZ LITE ADZS-BF592 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| ADZS-BF592-EZLITE | 制造商:Analog Devices 功能描述:ADZS-BF592-EZLITE |
| ADZS-BF608-EZLITE | 制造商:Analog Devices 功能描述:DIGITAL SIGNAL PROCESSOR - DEVELOPMENT TOOL |
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