参数资料
型号: ATMEGA103-6AI
厂商: Atmel
文件页数: 128/141页
文件大小: 0K
描述: IC MCU 128K 6MHZ A/D IT 64TQFP
产品培训模块: megaAVR Introduction
标准包装: 90
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 6MHz
连通性: SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 128KB(64K x 16)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-TQFP
包装: 托盘
配用: ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
87
ATmega103(L)
0945I–AVR–02/07
pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
Note:
n: 7,6...0, pin number
Port A Schematics
Note that all port pins are synchronized. The synchronization latch is, however, not
shown in the figure.
Figure 53. Port A Schematic Diagrams (Pins PA0 - PA7)
Port B
Port B is an 8-bit bi-directional I/O port with internal pull-ups.
Three I/O memory address locations are allocated for Port B, one each for the Data
Register – PORTB, $18($38), Data Direction Register – DDRB, $17($37) and the Port B
Input Pins – PINB, $16($36). The Port B Input Pins address is read-only, while the Data
Register and the Data Direction Register are read/write.
All port pins have individually selectable pull-up resistors. The Port B output buffers can
sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as
Table 28. DDAn Effects on Port A Pins
DDAn
PORTAn
I/O
Pull-up
Comment
0
Input
No
Tri-state (high-Z)
0
1
Input
Yes
PAn will source current if ext. pulled low.
1
0
Output
No
Push-pull Zero Output
1
Output
No
Push-pull One Output
DA
T
A
BUS
D
Q
RESET
C
WD
WP
RD
RP
MOS
PULL-
UP
PAn
R
WP:
WD:
RL:
RP:
RD:
SRE:
A:
D:
W:
R:
n:
WRITE PORTA
WRITE DDRA
READ PORTA LATCH
READ PORTA PIN
READ DDRA
EXT. SRAM ENABLE
ADDRESS
DATA
WRITE
READ
0-7
DDAn
PORTAn
SRE
R
Dn
W
An
RL
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